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A42L2604V-50UF PDF预览

A42L2604V-50UF

更新时间： 2024-01-13 00:51:48
品牌 Logo 应用领域
联笙电子 - AMICC /
页数 文件大小 规格书
25页 261K
描述
EDO DRAM, 4MX4, 50ns, CMOS, PDSO24

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A42L2604V-50UF 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：TSOP, TSOP24/26,.36Reach Compliance Code：unknown
风险等级：5.84最长访问时间：50 ns
I/O 类型：COMMONJESD-30 代码：R-PDSO-G24
内存密度：16777216 bit内存集成电路类型：EDO DRAM
内存宽度：4端子数量：24
字数：4194304 words字数代码：4000000
最高工作温度：85 °C最低工作温度：-40 °C
组织：4MX4输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP
封装等效代码：TSOP24/26,.36封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE电源：3.3 V
认证状态：Not Qualified刷新周期：2048
自我刷新：YES最大待机电流：0.001 A
子类别：DRAMs最大压摆率：0.075 mA
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUALBase Number Matches：1

A42L2604V-50UF 数据手册

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A42L2604 Series  
Selection Guide  
Symbol  
Description  
-45  
-50  
Unit  
tRAC  
45  
50  
ns  
Maximum RAS Access Time  
tAA  
Maximum Column Address Access Time  
Maximum CAS Access Time  
20  
12  
22  
13  
ns  
ns  
tCAC  
tOEA  
12  
13  
ns  
Maximum Output Enable ( OE) Access Time  
Minimum Read or Write Cycle Time  
Minimum EDO Cycle Time  
tRC  
tPC  
76  
18  
84  
20  
ns  
ns  
Functional Description  
The A42L2604 reads and writes data by multiplexing an  
22-bit address into a 11-bit(2K) row and column address.  
valid as long as RAS and OE are low, and WE is high;  
this is the only characteristic which differentiates Extended  
Data Out operation from a standard Read or Fast Page  
Read.  
and  
are used to strobe the row address and the  
CAS  
RAS  
column address, respectively.  
A Read cycle is performed by holding the WE signal high  
A memory cycle is terminated by returning both RAS and  
high. Memory cell data will retain its correct state by  
CAS  
during RAS/  
operation. A Write cycle is executed by  
CAS  
maintaining power and accessing all 2048(2K)  
combinations of the 11-bit(2K) row addresses, regardless  
holding the WE signal low during RAS /  
operation;  
CAS  
the input data is latched by the falling edge of WE or  
, whichever occurs later. The data inputs and outputs  
of sequence, at least once every 32ms through any RAS  
CAS  
are routed through 4 common I/O pins, with RAS,  
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,  
CBR, or Hidden). The CBR Refresh cycle automatically  
controls the row addresses by invoking the refresh counter  
and controller.  
,
CAS  
WE and OE controlling the in direction.  
EDO Page Mode operation all 2048(2K) columns within a  
selected row to be randomly accessed at a high data rate.  
A EDO Page Mode cycle is initiated with a row address  
Power-On  
The initial application of the VCC supply requires a 200 µs  
wait followed by a minimum of any eight initialization cycles  
latched by RAS followed by a column address latched by  
. While holding RAS low,  
can be toggled to  
CAS  
CAS  
containing a RAS clock. During Power-On, the VCC  
strobe changing column addresses, thus achieving shorter  
cycle times.  
current is dependent on the input levels of RAS and  
.
CAS  
The A42L2604 offers an accelerated Fast Page Mode  
cycle through a feature called Extended Data Out, which  
It is recommended that RAS and  
be held at a valid VIH during Power-On to avoid current  
surges.  
track with VCC or  
CAS  
keeps the output drivers on during the  
precharge  
CAS  
time (tcp). Since data can be output after  
goes high,  
CAS  
the user is not required to wait for valid data to appear  
before starting the next access cycle. Data-out will remain  
PRELIMINARY  
(June, 2002, Version 0.3)  
2
AMIC Technology, Inc.  
1234567...25

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