Datasheet > 存储 > DRAM> A42L2604V-50UF

A42L2604V-50UF

更新时间： 2024-01-15 12:39:56

品牌	Logo	应用领域
联笙电子 - AMICC		/
页数	文件大小	规格书
25页	261K
描述
EDO DRAM, 4MX4, 50ns, CMOS, PDSO24

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A42L2604V-50UF 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	TSOP, TSOP24/26,.36	Reach Compliance Code：	unknown
风险等级：	5.84	最长访问时间：	50 ns
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-G24
内存密度：	16777216 bit	内存集成电路类型：	EDO DRAM
内存宽度：	4	端子数量：	24
字数：	4194304 words	字数代码：	4000000
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	4MX4	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP
封装等效代码：	TSOP24/26,.36	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	电源：	3.3 V
认证状态：	Not Qualified	刷新周期：	2048
自我刷新：	YES	最大待机电流：	0.001 A
子类别：	DRAMs	最大压摆率：	0.075 mA
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

A42L2604V-50UF 数据手册

A42L2604 Series

Notes:

1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.

2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.

3. An initial pause of 200ms is required after power-up followed by any 8 RAS cycles before proper device operation is

achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of 8

RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.

4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and

50pF, VIL (min.) ³ GND and VIH (max.) £ VCC.

5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured

between VIH and VIL.

6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference

point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.

7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference

point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.

8. Assumes three state test load (5pF and a 500W Thevenin equivalent).

9. Either tRCH or tRRH must be satisfied for a read cycle.

10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output

voltage levels.

11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet

as electrical characteristics only. If tWCS ³ tWCS (min.) and tWCH ³ tWCH (min.), the cycle is an early write cycle

and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ³ tRWD (min.) , tCWD ³

tCWD (min.) and tAWD ³ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from

the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is

indeterminate.

12. Access time is determined by the longer of tAA or tCAC or tCPA.

13. tASC ³ tCP to achieve tPC (min.) and tCPA (max.) values.

PRELIMINARY

(June, 2002, Version 0.3)

AMIC Technology, Inc.

1...7 8 91011 12 13...25

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A42L8316SERIES	ETC	获取价格	256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
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A42L8316V-30	AMICC	获取价格	256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE

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