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A3PN010-2QNG48

更新时间： 2024-09-25 14:24:51
品牌 Logo 应用领域
ACTEL 栅可编程逻辑
页数 文件大小 规格书
106页 3324K
描述
Field Programmable Gate Array, 260 CLBs, 10000 Gates, 260-Cell, CMOS, 6 X 6 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-48

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A3PN010-2QNG48 技术参数

是否Rohs认证：符合生命周期：Transferred
包装说明：6 X 6 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-48Reach Compliance Code：compliant
风险等级：5.8Is Samacsys：N
JESD-30 代码：S-XQCC-N48JESD-609代码：e3
长度：6 mm可配置逻辑块数量：260
等效关口数量：10000输入次数：34
逻辑单元数量：260输出次数：34
端子数量：48最高工作温度：70 °C
最低工作温度：-20 °C组织：260 CLBS, 10000 GATES
封装主体材料：UNSPECIFIED封装代码：HQCCN
封装等效代码：LCC48,.24SQ,16封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG峰值回流温度（摄氏度）：260
电源：1.5,1.5/3.3 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified子类别：Field Programmable Gate Arrays
最大供电电压：1.575 V最小供电电压：1.425 V
标称供电电压：1.5 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：MATTE TIN端子形式：NO LEAD
端子节距：0.4 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：6 mm
Base Number Matches：1

A3PN010-2QNG48 数据手册

 浏览型号A3PN010-2QNG48的Datasheet PDF文件第2页浏览型号A3PN010-2QNG48的Datasheet PDF文件第3页浏览型号A3PN010-2QNG48的Datasheet PDF文件第4页浏览型号A3PN010-2QNG48的Datasheet PDF文件第5页浏览型号A3PN010-2QNG48的Datasheet PDF文件第6页浏览型号A3PN010-2QNG48的Datasheet PDF文件第7页 
Revision 8  
®
ProASIC3 nano Flash FPGAs  
Advanced I/Os  
Features and Benefits  
•
•
•
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Wide Range of Features  
Bank-Selectable I/O Voltages—up to 4 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V  
•
•
•
10 k to 250 k System Gates  
Up to 36 kbits of True Dual-Port SRAM  
Up to 71 User I/Os  
•
Wide Range Power Supply Voltage Support per JESD8-B,  
Allowing I/Os to Operate from 2.7 V to 3.6 V  
I/O Registers on Input, Output, and Enable Paths  
Selectable Schmitt Trigger Inputs  
Reprogrammable Flash Technology  
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS  
Process  
Hot-Swappable and Cold-Sparing I/Os  
•
•
•
Live at Power-Up (LAPU) Level 0 Support  
Single-Chip Solution  
Retains Programmed Design when Powered Off  
†
•
•
•
•
Programmable Output Slew Rate and Drive Strength  
Weak Pull-Up/-Down  
IEEE 1149.1 (JTAG) Boundary Scan Test  
Pin-Compatible Packages across the ProASIC3 Family  
High Performance  
•
350 MHz System Performance  
Clock Conditioning Circuit (CCC) and PLL†  
In-System Programming (ISP) and Security  
•
•
Up to Six CCC Blocks, One with an Integrated PLL  
Configurable Phase Shift, Multiply/Divide, Delay  
Capabilities and External Feedback  
•
Secure ISP Using On-Chip 128-Bit Advanced Encryption  
†
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)  
•
Wide Input Frequency Range (1.5 MHz to 350 MHz)  
®
•
FlashLock to Secure FPGA Contents  
Embedded Memory  
Low Power  
•
•
1 kbit of FlashROM User Nonvolatile Memory  
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM  
®
•
•
•
•
Low Power ProASIC 3 nano Products  
1.5 V Core Voltage for Low Power  
Support for 1.5 V-Only Systems  
Low-Impedance Flash Switches  
†
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)  
†
•
True Dual-Port SRAM (except ×18 organization)  
Enhanced Commercial Temperature Range  
High-Performance Routing Hierarchy  
•
–20°C to +70°C  
•
Segmented, Hierarchical Routing and Clock Structure  
Table 1 • ProASIC3 nano Devices  
ProASIC3 nano Devices  
ProASIC3 nano-Z Devices  
System Gates  
A3PN010  
A3PN015  
A3PN020  
A3PN060 A3PN125 A3PN250  
A3PN060Z A3PN125Z A3N250Z  
1
A3PN030Z  
10K  
86  
260  
–
15K  
128  
384  
–
20K  
172  
520  
–
30K  
256  
768  
–
60K  
512  
1,536  
18  
125K  
1,024  
3,072  
36  
250K  
2,048  
6,144  
36  
Typical Equivalent Macrocells  
VersaTiles (D-flip-flops)  
2
RAM kbits (1,024 bits)  
2
4,608-Bit Blocks  
–
–
–
–
4
8
8
FlashROM Bits  
1 k  
–
1 k  
–
1 k  
–
1 k  
–
1 k  
Yes  
1
1 k  
Yes  
1
1 k  
Yes  
1
2
Secure (AES) ISP  
2
Integrated PLL in CCCs  
–
–
–
–
VersaNet Globals  
4
4
4
6
18  
18  
18  
I/O Banks  
2
3
3
2
2
2
4
Maximum User I/Os (packaged device)  
Maximum User I/Os (Known Good Die)  
Package Pins  
34  
34  
49  
–
49  
52  
77  
83  
71  
71  
68  
71  
71  
68  
QFN  
VQFP  
QN48  
QN68  
QN68  
QN48, QN68  
VQ100  
VQ100  
VQ100  
VQ100  
Notes:  
1. A3PN030 is available in the Z feature grade only.  
2. A3PN030 and smaller devices do not support this feature.  
3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E handbooks.  
† A3PN030 and smaller devices do not support this feature.  
April 2010  
I
© 2010 Actel Corporation  
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