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A3PN010QN100PP

更新时间： 2024-09-25 12:41:19
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
114页 6102K
描述
ProASIC3 nano Flash FPGAs

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A3PN010QN100PP 数据手册

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Revision 11  
ProASIC3 nano Flash FPGAs  
Advanced I/Os  
Features and Benefits  
•
•
•
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages—up to 4 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V  
Wide Range of Features  
•
•
•
10 k to 250 k System Gates  
Up to 36 kbits of True Dual-Port SRAM  
Up to 71 User I/Os  
•
Wide Range Power Supply Voltage Support per JESD8-B,  
Allowing I/Os to Operate from 2.7 V to 3.6 V  
I/O Registers on Input, Output, and Enable Paths  
Selectable Schmitt Trigger Inputs  
Reprogrammable Flash Technology  
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS  
Process  
Hot-Swappable and Cold-Sparing I/Os  
•
•
•
Instant On Level 0 Support  
†
•
•
•
•
Programmable Output Slew Rate and Drive Strength  
Single-Chip Solution  
Retains Programmed Design when Powered Off  
Weak Pull-Up/-Down  
IEEE 1149.1 (JTAG) Boundary Scan Test  
Pin-Compatible Packages across the ProASIC3 Family  
High Performance  
•
350 MHz System Performance  
Clock Conditioning Circuit (CCC) and PLL†  
In-System Programming (ISP) and Security  
•
•
Up to Six CCC Blocks, One with an Integrated PLL  
Configurable Phase Shift, Multiply/Divide, Delay  
Capabilities and External Feedback  
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard  
†
(AES) Decryption via JTAG (IEEE 1532–compliant)  
®
•
Wide Input Frequency Range (1.5 MHz to 350 MHz)  
•
FlashLock Designed to Secure FPGA Contents  
Embedded Memory  
Low Power  
®
•
•
1 kbit of FlashROM User Nonvolatile Memory  
•
•
•
•
Low Power ProASIC 3 nano Products  
1.5 V Core Voltage for Low Power  
Support for 1.5 V-Only Systems  
Low-Impedance Flash Switches  
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM  
†
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)  
†
•
True Dual-Port SRAM (except ×18 organization)  
High-Performance Routing Hierarchy  
Enhanced Commercial Temperature Range  
•
Segmented, Hierarchical Routing and Clock Structure  
•
–20°C to +70°C  
Table 1 • ProASIC3 nano Devices  
ProASIC3 nano Devices  
ProASIC3 nano-Z Devices1  
System Gates  
A3PN010 A3PN0151 A3PN020  
A3PN060  
A3PN125  
A3PN250  
A3N250Z1  
A3PN030Z1,2 A3PN060Z1 A3PN125Z1  
10,000  
15,000  
20,000  
30,000  
60,000  
512  
1,536  
18  
125,000  
250,000  
Typical Equivalent Macrocells  
VersaTiles (D-flip-flops)  
86  
260  
–
128  
384  
–
172  
520  
–
256  
768  
–
1,024  
3,072  
36  
8
2,048  
6,144  
36  
8
2
RAM Kbits (1,024 bits)  
2
4,608-Bit Blocks  
–
–
–
–
4
FlashROM Kbits  
1
1
1
1
1
1
1
2
Secure (AES) ISP  
–
–
–
–
Yes  
1
Yes  
1
Yes  
1
2
Integrated PLL in CCCs  
–
–
–
–
VersaNet Globals  
4
4
4
6
18  
18  
2
18  
4
I/O Banks  
2
3
3
2
2
Maximum User I/Os (packaged device)  
Maximum User I/Os (Known Good Die)  
Package Pins  
34  
34  
49  
–
49  
52  
77  
83  
71  
71  
71  
68  
68  
71  
QFN  
VQFP  
QN48  
QN68  
QN68  
QN48, QN68  
VQ100  
VQ100  
VQ100  
VQ100  
Notes:  
1. Not recommended for new designs.  
2. A3PN030Z and smaller devices do not support this feature.  
3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E datasheets.  
† A3PN030 and smaller devices do not support this feature.  
January 2013  
I
© 2013 Microsemi Corporation  
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