v1.0
®
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
®
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Features and Benefits
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
High Capacity
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
†
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• I/O Registers on Input, Output, and Enable Paths
‡
• Hot-Swappable and Cold Sparing I/Os
†
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
• Retains Programmed Design when Powered Off
High Performance
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• 350 MHz System Performance
†
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• Configurable
Phase-Shift,
Multiply/Divide,
Delay
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
®
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
Standard (AES) Decryption (except ARM-enabled ProASIC 3
†
devices) via JTAG (IEEE 1532–compliant)
®
• FlashLock to Secure FPGA Contents
• 1 kbit of FlashROM User Nonvolatile Memory
Low Power
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
• Core Voltage for Low Power
†
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
• M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft
Processor Available with or without Debug
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
ProASIC3 Product Family
ProASIC3 Devices
A3P015 A3P030 A3P060 A3P125
A3P250
A3P400
A3P600
A3P1000
1
ARM7 Devices
M7A3P1000
1
Cortex-M1 Devices
System Gates
M1A3P250
M1A3P400
M1A3P600
M1A3P1000
15 k
128
384
–
30 k
256
768
–
60 k
512
1,536
18
125 k
1,024
3,072
36
250 k
–
400 k
–
600 k
–
1 M
–
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
6,144
36
9,216
54
13,824
108
24
24,576
144
32
–
–
4
8
8
12
FlashROM Bits
1 k
–
1 k
–
1 k
Yes
1
1 k
Yes
1
1 k
Yes
1
1 k
Yes
1
1 k
Yes
1
1 k
Yes
1
2
Secure (AES) ISP
Integrated PLL in CCCs
–
–
3
VersaNet Globals
6
6
18
18
18
18
18
18
I/O Banks
2
2
2
2
4
4
4
4
Maximum User I/Os
49
81
96
133
157
194
235
300
Package Pins
QFN
5
QN68
QN132 QN132 QN132
QN132
VQFP
VQ100
VQ100
TQ144
VQ100
TQ144
PQ208
VQ100
TQFP
PQFP
PQ208
FG144 FG144/256
PQ208
FG144/256/
484
PQ208
FG144/256/
484
PQ208
FG144/256/
484
5
FBGA
FG144
Notes:
1. Refer to the CoreMP7 datasheet or Cortex-M1 product brief for more information.
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs handbook.
5. The M1A3P250 device does not support this package.
†
A3P015 and A3P030 devices do not support this feature.
‡ Supported only by A3P015 and A3P030 devices.
February 2008
I
© 2008 Actel Corporation
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