DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
ELECTRICAL CHARACTERISTICS1 valid at TA=25°C, VBB = 50 V, fPWM < 50 kHz, unless otherwise noted
Characteristic
Output Drivers
Symbol
Test Conditions
Min.
Typ.2
Max.
Units
Operating, IOUT = ±1.5 A
During Sleep mode
VOUT = VBB
15
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
50
50
50
–50
0.6
0.6
1.2
1.2
8
6
20
12
10
V
V
μA
ꢀA
Ω
Ω
V
V
mA
mA
ꢀA
mA
mA
mA
ꢀA
Load Supply Voltage Range
Output Leakage Current
Output On Resistance
VBB
IDSS
RDS(on)
VF
<1.0
<–1.0
0.54
0.54
–
–
–
–
–
–
–
–
–
VOUT = 0 V
Source driver, IOUT = -1.5 A
Sink driver, IOUT = 1.5 A
Source diode, IF = -1.5 A
Sink diode, IF = 1.5 A
fPWM < 50 kHz
Operating, outputs disabled
Sleep or Idle mode
fPWM < 50 kHz
Body Diode Forward Voltage
Motor Supply Current
Logic Supply Current
IBB
Outputs off
Idle mode (Word 1, D18 = 0)
Sleep mode
IDD
1.5
100
Control Logic
Logic Supply Voltage Range
VDD
VIN(1)
VIN(0)
IIN(1)
IIN(0)
Operating
4.5
2.0
–
–
–
0.20
> 2
2.5
40
5
–
–
5.5
–
0.8
20
–20
0.40
–
V
V
V
μA
μA
V
μs
MHz
%
Logic Input Voltage
Logic Input Current
VIN = 2.0 V
VIN = 0.8 V
<1.0
<–2.0
–
–
–
Input Hysteresis
Minimum sleep pulse width
OSC input frequency
OSC input duty cycle
tS
fOSC(in)
Divide by 1 (Word 2, D13=0, D14=1)
6
60
–
OSC shorted to GND
ROSC= 51 kꢁ
Measured relative to REF buffer output
3
3.4
–
.5
–
7.4
3.6
–0.5
1.940
–5
4
4
±0.5
–
±10
8
4
–
2.0
0
0
0
0
0
800
–
800
–
650
4.2
0.10
5
4.6
–
2.6
–
8.8
4.4
0.5
2.060
5
6
9
6
10
1000
250
1000
250
900
4.45
–
MHz
MHz
LSB
V
mV
–
–
ꢀA
V
mV
%
%
%
%
ns
ns
ns
ns
ns
V
Internal Oscillator
fOSC
DAC Accuracy
Reference Input Voltage Range
Reference Buffer Offset
VDAC
VOS
Word 0, D18 = 0, D17 = 1, VREF = 0.5 to 2.6 V
Word 0, D18 = 1, D17 = 1, VREF =0.5 to 2.6 V
VREF = 2.0 V
Reference Divider Ratio
VREF/VSENSE
Reference Input Current
Internal Reference Voltage
Comparator Input Offset Volt.
IREF
VREFINT
VIO
VREF = 0 V
Internal VREF, Range = 8, DAC = 63
Internal VREF, Range = 8, DAC = 31
Internal VREF, Range = 4, DAC = 63
Internal VREF, Range = 4, DAC = 15
50% to 90%; PWM change to source on
50% to 90%; PWM change to source off
50% to 90%; PWM change to sink on
50% to 90%; PWM change to sink off
–6
–9
–6
GM Error3
VERR
–10
500
35
500
35
300
3.9
0.05
Propagation Delay Times
t
pd
Crossover Dead Time
UVLO Enable Threshold
UVLO Hysteresis
tDT
VUVLO
VUVLOHYS
VDD rising
V
Protection Circuitry
Overcurrent Protection Threshold4
Overcurrent Blanking
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
IOCPST
tOCP
TJ
2
1
–
–
–
–
165
15
–
3
–
–
A
μs
°C
°C
TJHYS
1Negative current is defined as coming out of (sourcing) the specified device pin.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3VERR = [(VREF/Range) – VSENSE] /(VREF/Range).
4OCP is tested at TA = 25°C in a restricted range and guaranteed by characterization.
Allegro MicroSystems, LLC
4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com