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A3992SB-T PDF预览

A3992SB-T

更新时间: 2024-02-23 18:56:23
品牌 Logo 应用领域
急速微 - ALLEGRO 电动机控制光电二极管
页数 文件大小 规格书
13页 588K
描述
Stepper Motor Controller, 1.5A, NMOS, PDIP24, LEAD FREE, PLASTIC, MS-001BE, DIP-24

A3992SB-T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP24,.3针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:8.5
其他特性:ALSO REQUIRES 15V TO 50V VBB SUPPLY模拟集成电路 - 其他类型:STEPPER MOTOR CONTROLLER
JESD-30 代码:R-PDIP-T24JESD-609代码:e3
长度:30.1 mm功能数量:1
端子数量:24最高工作温度:85 °C
最低工作温度:-20 °C最大输出电流:1.5 A
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP24,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:50 V认证状态:Not Qualified
座面最大高度:5.33 mm子类别:Motion Control Electronics
最大供电电流 (Isup):12 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:NMOS
温度等级:OTHER端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

A3992SB-T 数据手册

 浏览型号A3992SB-T的Datasheet PDF文件第1页浏览型号A3992SB-T的Datasheet PDF文件第2页浏览型号A3992SB-T的Datasheet PDF文件第3页浏览型号A3992SB-T的Datasheet PDF文件第5页浏览型号A3992SB-T的Datasheet PDF文件第6页浏览型号A3992SB-T的Datasheet PDF文件第7页 
DMOS Dual Full-Bridge  
Microstepping PWM Motor Driver  
A3992  
ELECTRICAL CHARACTERISTICS1 valid at TA=25°C, VBB = 50 V, fPWM < 50 kHz, unless otherwise noted  
Characteristic  
Output Drivers  
Symbol  
Test Conditions  
Min.  
Typ.2  
Max.  
Units  
Operating, IOUT = ±1.5 A  
During Sleep mode  
VOUT = VBB  
15  
0
50  
50  
50  
–50  
0.6  
0.6  
1.2  
1.2  
8
6
20  
12  
10  
V
V
μA  
A  
Ω
Ω
V
V
mA  
mA  
A  
mA  
mA  
mA  
A  
Load Supply Voltage Range  
Output Leakage Current  
Output On Resistance  
VBB  
IDSS  
RDS(on)  
VF  
<1.0  
<–1.0  
0.54  
0.54  
VOUT = 0 V  
Source driver, IOUT = -1.5 A  
Sink driver, IOUT = 1.5 A  
Source diode, IF = -1.5 A  
Sink diode, IF = 1.5 A  
fPWM < 50 kHz  
Operating, outputs disabled  
Sleep or Idle mode  
fPWM < 50 kHz  
Body Diode Forward Voltage  
Motor Supply Current  
Logic Supply Current  
IBB  
Outputs off  
Idle mode (Word 1, D18 = 0)  
Sleep mode  
IDD  
1.5  
100  
Control Logic  
Logic Supply Voltage Range  
VDD  
VIN(1)  
VIN(0)  
IIN(1)  
IIN(0)  
Operating  
4.5  
2.0  
0.20  
> 2  
2.5  
40  
5
5.5  
0.8  
20  
–20  
0.40  
V
V
V
μA  
μA  
V
μs  
MHz  
%
Logic Input Voltage  
Logic Input Current  
VIN = 2.0 V  
VIN = 0.8 V  
<1.0  
<–2.0  
Input Hysteresis  
Minimum sleep pulse width  
OSC input frequency  
OSC input duty cycle  
tS  
fOSC(in)  
Divide by 1 (Word 2, D13=0, D14=1)  
6
60  
OSC shorted to GND  
ROSC= 51 kꢁ  
Measured relative to REF buffer output  
3
3.4  
.5  
7.4  
3.6  
–0.5  
1.940  
–5  
4
4
±0.5  
±10  
8
4
2.0  
0
0
0
0
0
800  
800  
650  
4.2  
0.10  
5
4.6  
2.6  
8.8  
4.4  
0.5  
2.060  
5
6
9
6
10  
1000  
250  
1000  
250  
900  
4.45  
MHz  
MHz  
LSB  
V
mV  
A  
V
mV  
%
%
%
%
ns  
ns  
ns  
ns  
ns  
V
Internal Oscillator  
fOSC  
DAC Accuracy  
Reference Input Voltage Range  
Reference Buffer Offset  
VDAC  
VOS  
Word 0, D18 = 0, D17 = 1, VREF = 0.5 to 2.6 V  
Word 0, D18 = 1, D17 = 1, VREF =0.5 to 2.6 V  
VREF = 2.0 V  
Reference Divider Ratio  
VREF/VSENSE  
Reference Input Current  
Internal Reference Voltage  
Comparator Input Offset Volt.  
IREF  
VREFINT  
VIO  
VREF = 0 V  
Internal VREF, Range = 8, DAC = 63  
Internal VREF, Range = 8, DAC = 31  
Internal VREF, Range = 4, DAC = 63  
Internal VREF, Range = 4, DAC = 15  
50% to 90%; PWM change to source on  
50% to 90%; PWM change to source off  
50% to 90%; PWM change to sink on  
50% to 90%; PWM change to sink off  
–6  
–9  
–6  
GM Error3  
VERR  
–10  
500  
35  
500  
35  
300  
3.9  
0.05  
Propagation Delay Times  
t
pd  
Crossover Dead Time  
UVLO Enable Threshold  
UVLO Hysteresis  
tDT  
VUVLO  
VUVLOHYS  
VDD rising  
V
Protection Circuitry  
Overcurrent Protection Threshold4  
Overcurrent Blanking  
Thermal Shutdown Temperature  
Thermal Shutdown Hysteresis  
IOCPST  
tOCP  
TJ  
2
1
165  
15  
3
A
μs  
°C  
°C  
TJHYS  
1Negative current is dened as coming out of (sourcing) the specied device pin.  
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for  
individual units, within the specied maximum and minimum limits.  
3VERR = [(VREF/Range) – VSENSE] /(VREF/Range).  
4OCP is tested at TA = 25°C in a restricted range and guaranteed by characterization.  
Allegro MicroSystems, LLC  
4
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
www.allegromicro.com  

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