Datasheet > A3992SB-T

A3992SB-T

更新时间： 2024-02-17 12:32:39

品牌	Logo	应用领域
急速微 - ALLEGRO		电动机控制光电二极管
页数	文件大小	规格书
13页	588K
描述
Stepper Motor Controller, 1.5A, NMOS, PDIP24, LEAD FREE, PLASTIC, MS-001BE, DIP-24

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技术参数
数据手册

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A3992SB-T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP, DIP24,.3	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	8.5
其他特性：	ALSO REQUIRES 15V TO 50V VBB SUPPLY	模拟集成电路 - 其他类型：	STEPPER MOTOR CONTROLLER
JESD-30 代码：	R-PDIP-T24	JESD-609代码：	e3
长度：	30.1 mm	功能数量：	1
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-20 °C	最大输出电流：	1.5 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP24,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	50 V	认证状态：	Not Qualified
座面最大高度：	5.33 mm	子类别：	Motion Control Electronics
最大供电电流 (Isup)：	12 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	NMOS
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

A3992SB-T 数据手册

DMOS Dual Full-Bridge

Microstepping PWM Motor Driver

A3992

Word 1 Bit Assignments

from erroneously resetting the source enable latch,

the sense comparator is blanked. The blank timer runs

after the off time counter to provide the programmable

blanking function. The blank timer is reset when

PHASE is changed.

Word 1 is selected by setting D0 = 1. Assignments are

summarized in the following table, and described in

detail in the remainder of this section.

Word 1 Bit Assignments

Bit

Function

Word Select = 1

Blank Time LSB

Blank Time MSB

Off Time LSB

D3 – D7 Fixed Off Time. 5 bits to set the ﬁxed

off-time for the internal PWM control circuitry. Fixed

off-time is deﬁned by:

t_OFF= (1 + n) × P_OSC× 8 – P_{OSC ,}

where n = 0 to 31.

Off Time Bit1

For example, with a master oscillator frequency of

4 MHz ( P_OSC= 250 ns), the ﬁxed off-time is adjust-

able from 1.75 to 63.75 μs, in increments of 2 μs.

Off Time Bit2

Off Time Bit3

Off Time MSB

D8 – D11 Fast Decay Time. 4 bits to set the fast

decay portion of ﬁxed off-time for the internal PWM

control circuitry. The fast decay portion is deﬁned by:

t_fd= (1 + n) × P_OSC× 8 – P_{OSC ,}

Fast Decay Time LSB

Fast Decay Time Bit1

Fast Decay Time Bit2

Fast Decay Time MSB

C0 Oscillator Control

C1 Oscillator Control

SR Control Bit 1

SR Control Bit 2

Reserved for testing

Idle Mode

D10

D11

D12

D13

D14

D15

D16

D17

D18

where n = 0 to 15.

For example, with a master oscillator frequency of

4 MHz ( P_OSC= 250 ns), the ﬁxed off-time is adjust-

able from 1.75 to 31.75 μs, in increments of 2 μs. For

t_fd> t_off, the device will effectively operate in fast

decay mode.

D12 – D13 Oscillator Control. 2 bits to set timing

options:

D1 – D2 Blank Time. 2 bits to set the blank time scal-

D13

D12

Source and Rate

Internal clock 4 MHz

External clock f ÷ 1

External clock f ÷ 2

External clock f ÷ 4

ing factor for the current sense comparator:

Time

4 × P_OSC

6 × P_OSC

8 × P_OSC

12 × P_OSC

A 4 MHz internal oscillator can be used for the tim-

ing functions. If more precise control is required, an

external oscillator can be input to OSC pin. To accom-

modate a wider range of system clocks, an internal

divider is provided to generate the desired MO fre-

quency.

When a source driver turns on, a current spike occurs

due to the reverse recovery currents of the clamp di-

odes and/or switching transients related to distributed

capacitance in the load. To prevent this current spike

Allegro MicroSystems, LLC

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

1...3 4 567 8 9...13

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