Datasheet > 驱动程序和接口 > MOSFET 驱动器> A3941KLPTR-T

A3941KLPTR-T

更新时间： 2024-02-03 20:38:38

品牌	Logo	应用领域
急速微 - ALLEGRO		驱动器 MOSFET驱动器驱动程序和接口接口集成电路光电二极管 PC
页数	文件大小	规格书
20页	524K
描述
Automotive Full Bridge MOSFET Driver

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技术参数
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A3941KLPTR-T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP-28	针数：	28
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.54
Samacsys Confidence：	3	Samacsys Status：	Released
Samacsys PartID：	549291	Samacsys Pin Count：	29
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Small Outline Packages
Samacsys Footprint Name：	TSSOP_28	Samacsys Released Date：	2019-11-29 17:04:57
Is Samacsys：	N	高边驱动器：	YES
接口集成电路类型：	FULL BRIDGE BASED MOSFET DRIVER	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	长度：	9.7 mm
湿度敏感等级：	2	功能数量：	1
端子数量：	28	最高工作温度：	150 °C
最低工作温度：	-40 °C	标称输出峰值电流：	0.028 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	HTSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压：	50 V
最小供电电压：	5.5 V	标称供电电压：	12 V
表面贴装：	YES	温度等级：	AUTOMOTIVE
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	断开时间：	0.15 µs
接通时间：	0.15 µs	宽度：	4.4 mm
Base Number Matches：	1

A3941KLPTR-T 数据手册

A3941

Automotive Full Bridge MOSFET Driver

In some applications a safety resistor is added between the gate

and source of each FET in the bridge. When a high-side FET is

held in the on-state, the current through the associated high-side

LSS Pin This is the low-side return path for discharge of the

capacitance on the FET gates. It should be tied directly to the

common sources of the low-side external FETs through an inde-

gate-source resistor (R_GSH) is provided by the high-side drive and pendent low impedance connection.

therefore appears as a static resistive load on the top-off charge

RDEAD Pin This pin controls internal generation of dead time

during FET switching.

pump. The minimum value of R_GSHfor which the top-off charge

pump can provide current is shown in the Electrical Characteris-

tics table.

• When a resistor greater than 3 kΩ is connected between

RDEAD and AGND, cross-conduction is prevented by the gate

drive circuits, which introduce a dead time, t_DEAD, between

switching one FET off and the complementary FET on. The

dead time is derived from the resistor value connected between

the RDEAD and AGND pins.

• When RDEAD is connected directly to V5, cross-conduction is

prevented by the gate drive circuits. In this case, t_DEADdefaults

to a value of 6 μs typical.

GLA and GLB Pins These are the low-side gate drive outputs for

the external N-channel MOSFETs. External resistors between the

gate drive output and the gate connection to the FET (as close as

possible to the FET) can be used to control the slew rate seen at

the gate, thereby providing some control of the di/dt and dv/dt of

the SA and SB outputs. GLx going high turns on the upper half of

the drive, sourcing current to the gate of the low-side FET in the

external power bridge, turning it on. GLx going low turns on the

lower half of the drive, sinking current from the external FET gate

circuit to the LSS pin, turning off the FET.

Logic Control Inputs

SA and SB Pins Directly connected to the motor, these terminals

sense the voltages switched across the load. These terminals are

also connected to the negative side of the bootstrap capacitors

and are the negative supply connections for the floating high-side

drives. The discharge current from the high-side FET gate capaci-

tance flows through these connections, which should have low

impedance circuit connections to the FET bridge.

Four low-voltage level digital inputs provide control for the

gate drives. These logic inputs all have a nominal hysteresis of

500 mV to improve noise performance. They are used together

to provide fast decay or slow decay with high-side or low-side

recirculation. They also provide brake, coast, and sleep modes as

defined in tables 1 and 2.

PWMH and PWML Pins These inputs can be used to control

current in the power bridge. PWMH provides high-side chopping

and PWML provides low-side chopping. When used together

they control the power bridge in fast decay mode. The PWM

options are provided in table 2.

GHA and GHB Pins These terminals are the high-side gate

drive outputs for the external N-channel FETs. External resistors

between the gate drive output and the gate connection to the FET

(as close as possible to the FET) can be used to control the slew

rate seen at the gate, thereby controlling the di/dt and dv/dt of the

SA and SB outputs. GHx going high turns on the upper half of

the drive, sourcing current to the gate of the high-side FET in the

external motor-driving bridge, turning it on. GHx going low turns

on the lower half of the drive, sinking current from the external

FET gate circuit to the corresponding Sx pin, turning off the FET.

• Setting PWMH low turns off active high-side drives. This

provides high-side–chopped slow-decay PWM.

• Setting PWML low turns off active low-side drives. This

provides low-side–chopped slow-decay PWM.

• PWMH and PWML may also be connected together and driven

with a single PWM signal. This provides fast-decay PWM.

CA and CB Pins These are the high-side connections for the

bootstrap capacitors and are the positive supply for the high-side

gate drives. The bootstrap capacitors are charged to approxi-

mately V_REGwhen the associated output Sx terminal is low.

When the Sx output swings high, the charge on the bootstrap

capacitor causes the voltage at the corresponding Cx terminal to

rise with the output to provide the boosted gate voltage needed

for the high-side FETs.

PHASE Pin The state of the PHASE pin determines the positive

direction of load current (see table 1). The PHASE pin can also

be used as a PWM input when full four-quadrant control (fast

decay synchronous rectification) is required (see table 2).

SR Pin This enables or disables synchronous rectification. When

SR is high, synchronous rectification is enabled. When a PWM-

off phase occurs (low on either or both of the PWMH and PWML

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

1...5 6 789 10 11...20

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A3941KLPTR-T 替代型号

型号	品牌	替代类型	描述	数据表
A3940KLPTR-T	ALLEGRO	类似代替	Full Bridge Based MOSFET Driver, 0.8A, PDSO28, TSSOP-28
A3940KLP-T	ALLEGRO	类似代替	FULL-BRIDGE POWER MOSFET CONTROLLER
A3940KLP	ALLEGRO	类似代替	FULL-BRIDGE POWER MOSFET CONTROLLER

与A3941KLPTR-T相关器件

型号	品牌	获取价格	描述	数据表
A3942	ALLEGRO	获取价格	Quad High-Side Gate Driver
A3942KLG-T	ALLEGRO	获取价格	Buffer/Inverter Based Peripheral Driver, PDSO38, 1.20 MM HEIGHT, LEAD FREE, MO-153BD-1, TS
A3942KLGTR-T	ALLEGRO	获取价格	Buffer/Inverter Based Peripheral Driver, PDSO38, TSSOP-38
A3944	ALLEGRO	获取价格	Automotive, Low-Side FET Pre-Driver
A3944KLPTR-T	ALLEGRO	获取价格	Buffer/Inverter Based MOSFET Driver, PDSO28, LEAD FREE, TSSOP-28
A3946	ALLEGRO	获取价格	Half-Bridge Power MOSFET Controller
A3946KLB	ALLEGRO	获取价格	Half-Bridge Power MOSFET Controller
A3946KLB-T	ALLEGRO	获取价格	Half-Bridge Power MOSFET Controller
A3946KLBTR	ALLEGRO	获取价格	Half-Bridge Power MOSFET Controller
A3946KLBTR-T	ALLEGRO	获取价格	Half-Bridge Power MOSFET Controller

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