Datasheet > A32100DX-1BG225C

A32100DX-1BG225C

更新时间： 2024-02-24 23:28:35

品牌	Logo	应用领域
ACTEL		栅可编程逻辑
页数	文件大小	规格书
22页	207K
描述
Field Programmable Gate Array, 700 CLBs, 10000 Gates, CMOS, PBGA225, BGA-225

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技术参数
数据手册

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A32100DX-1BG225C 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	BGA-225	Reach Compliance Code：	compliant
风险等级：	5.9	Is Samacsys：	N
JESD-30 代码：	S-PBGA-B225	JESD-609代码：	e0
长度：	27 mm	可配置逻辑块数量：	700
等效关口数量：	10000	端子数量：	225
最高工作温度：	70 °C	最低工作温度：
组织：	700 CLBS, 10000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD SILVER	端子形式：	BALL
端子节距：	1.5 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	27 mm
Base Number Matches：	1

A32100DX-1BG225C 数据手册

I/O Mo d u le s

segments. The minimum horizontal segment length is the

width of a module-pair, and the maximum horizontal

segment length is the full length of the channel. Any segment

that spans more than one-third the row length is considered a

long horizontal segment. A typical channel is shown in

Figure 6. Non-dedicated horizontal routing tracks are used to

route signal nets. Dedicated routing tracks are used for the

global clock networks and for power and ground tie-off

tracks.

The I/O modules provide the interface between the device

pins and the logic array (shown in Figure 5). A variety of I/O

configurations, determined by a library macro selection, can

be implemented in the module (refer to the Macro Library

Guide for more information). I/O modules contain input and

output latches as well as a tri-state buffer. These features

allow the module to be configured for input, output, or

bi-directional pins.

Vertical Routing

Other tracks run vertically through the module. Vertical

tracks are of three types: input, output, and long. Vertical

tracks are also divided into one or more segments. Each

segment in an input track is dedicated to the input of a

particular module. Each segment in an output track is

dedicated to the output of a particular module. Long segments

are uncommitted and can be assigned during routing. Each

output segment spans four channels (two above and two

below), except near the top and bottom of the array where

edge effects occur. An example of vertical routing tracks and

segments is shown in Figure 6.

PAD

From Array

G/CLK*

To Array

Segmented

Logic

G/CLK*

horizontal

Modules

routing

tracks

* Can be conﬁgured as a Latch or D Flip-Flop

(using C-module)

Figure 5 • I/O Module

Antifuses

I/O modules contain input and output latches for capturing

data prior to and/or from the device pins. In addition, the

Actel Designer Series software tools can build a D flip-flop

using a C-module in conjunction with the I/O latch to register

input and/or output signals. Actel’s Designer Series

development tools provide a design library of I/O macros

which can implement all I/O configurations supported by the

3200DX.

Vertical routing tracks

Figure 6 • Horizontal Routing Tracks and Segments

Antifuse Structures

R o u t in g S t r u c t u r e

An antifuse is a “normally open” structure as opposed to the

normally closed fuse structure used in PROMs or PALs. The

use of antifuses to implement a Programmable Logic Device

results in highly testable structures as well as efficient

programming algorithms. The structure is highly testable

because there are no pre-existing connections; therefore,

temporary connections can be made using pass transistors.

These temporary connections can isolate individual antifuses

to be programmed as well as isolate individual circuit

structures to be tested. This can be done both before and after

programming. For example, all metal tracks can be tested for

continuity and shorts between adjacent tracks, and the

functionality of all logic modules can be verified.

The 3200DX architecture uses Horizontal and Vertical

routing tracks to interconnect the various logic and I/O

modules. These routing tracks are metal interconnects that

may either be of continuous length or broken into pieces

called segments. Varying segment lengths allows the

interconnect of over 90% of design tracks to occur with only

two antifuse connections. Segments can be joined together at

the ends, using antifuses, to increase their lengths up to the

full length of the track. All interconnects can be

accomplished with a maximum of four antifuses.

Horizontal Routing

Horizontal channels are located between the rows of modules

and are composed of several routing tracks. The horizontal

routing tracks within the channel are divided into one or more

1...3 4 567 8 9...22

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与A32100DX-1BG225C相关器件

型号	品牌	获取价格	描述	数据表
A32100DX-1BGG225C	ACTEL	获取价格	Field Programmable Gate Array, 700 CLBs, 10000 Gates, CMOS, PBGA225, BGA-225
A32100DX-1BGG225I	ACTEL	获取价格	Field Programmable Gate Array, 700 CLBs, 10000 Gates, CMOS, PBGA225, BGA-225
A32100DX-1CQ84B	ACTEL	获取价格	Highly Predictable Performance with 100% Automatic Placement and Routing
A32100DX-1CQ84C	MICROSEMI	获取价格	Field Programmable Gate Array, 1362-Cell, CMOS, CQFP84,
A32100DX-1CQ84M	MICROSEMI	获取价格	Field Programmable Gate Array, 146MHz, 1362-Cell, CMOS, CQFP84,
A32100DX-1CQB	ACTEL	获取价格	Integrator Series FPGAs: 1200XL and 3200DX Families
A32100DX-1CQC	ACTEL	获取价格	Integrator Series FPGAs: 1200XL and 3200DX Families
A32100DX-1CQG84B	ACTEL	获取价格	Field Programmable Gate Array, 1382 CLBs, 10000 Gates, 146MHz, CMOS, CQFP84, CERAMIC, QFP-
A32100DX-1CQG84C	ACTEL	获取价格	Field Programmable Gate Array, 1382 CLBs, 10000 Gates, CMOS, PQFP84, CERAMIC, QFP-84
A32100DX-1PGB	ACTEL	获取价格	Integrator Series FPGAs: 1200XL and 3200DX Families

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