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A2F060M3E-FG256YC PDF预览

A2F060M3E-FG256YC

更新时间: 2024-01-02 10:55:16
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
192页 11779K
描述
FPGA

A2F060M3E-FG256YC 技术参数

生命周期:Obsolete包装说明:1 MM PITCH, FBGA-256
Reach Compliance Code:unknown风险等级:5.76
Is Samacsys:NJESD-30 代码:S-PBGA-B256
长度:17 mm可配置逻辑块数量:1536
等效关口数量:60000端子数量:256
组织:1536 CLBS, 60000 GATES封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:1.7 mm
最大供电电压:1.575 V最小供电电压:1.425 V
标称供电电压:1.5 V表面贴装:YES
技术:CMOS端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:17 mmBase Number Matches:1

A2F060M3E-FG256YC 数据手册

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1 – SmartFusion Family Overview  
Introduction  
The SmartFusion® family of cSoCs builds on the technology first introduced with the Fusion mixed signal  
FPGAs. SmartFusion cSoCs are made possible by integrating FPGA technology with programmable  
high-performance analog and hardened ARM Cortex-M3 microcontroller blocks on a flash semiconductor  
process. The SmartFusion cSoC takes its name from the fact that these three discrete technologies are  
integrated on a single chip, enabling the lowest cost of ownership and smallest footprint solution to you.  
General Description  
Microcontroller Subsystem (MSS)  
The MSS is composed of a 100 MHz Cortex-M3 processor and integrated peripherals, which are  
interconnected via a multi-layer AHB bus matrix (ABM). This matrix allows the Cortex-M3 processor,  
FPGA fabric master, Ethernet message authentication controller (MAC), when available, and peripheral  
DMA (PDMA) controller to act as masters to the integrated peripherals, FPGA fabric, embedded  
nonvolatile memory (eNVM), embedded synchronous RAM (eSRAM), external memory controller  
(EMC), and analog compute engine (ACE) blocks.  
SmartFusion cSoCs of different densities offer various sets of integrated peripherals. Available  
peripherals include SPI, I2C, and UART serial ports, embedded FlashROM (EFROM), 10/100 Ethernet  
MAC, timers, phase-locked loops (PLLs), oscillators, real-time counters (RTC), and peripheral DMA  
controller (PDMA).  
Programmable Analog  
Analog Front-End (AFE)  
SmartFusion cSoCs offer an enhanced analog front-end compared to Fusion devices. The successive  
approximation register analog-to-digital converters (SAR ADC) are similar to those found on Fusion  
devices. SmartFusion cSoC also adds first order sigma-delta digital-to-analog converters (SDD DAC).  
SmartFusion cSoCs can handle multiple analog signals simultaneously with its signal conditioning blocks  
(SCBs). SCBs are made of a combination of active bipolar prescalers (ABPS), comparators, current  
monitors and temperature monitors. ABPS modules allow larger bipolar voltages to be fed to the ADC.  
Current monitors take the voltage across an external sense resistor and convert it to a voltage suitable  
for the ADC input range. Similarly, the temperature monitor reads the current through an external PN-  
junction (diode or transistor) and converts it internally for the ADC. The SCB also includes comparators  
to monitor fast signal thresholds without using the ADC. The output of the comparators can be fed to the  
analog compute engine or the ADC.  
Analog Compute Engine (ACE)  
The mixed signal blocks found in SmartFusion cSoCs are controlled and connected to the rest of the  
system via a dedicated processor called the analog compute engine (ACE). The role of the ACE is to  
offload control of the analog blocks from the Cortex-M3, thus offering faster throughput or better power  
consumption compared to a system where the main processor is in charge of monitoring the analog  
resources. The ACE is built to handle sampling, sequencing, and post-processing of the ADCs, DACs,  
and SCBs.  
Revision 10  
1-1  

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