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A29DL163TV-70UF PDF预览

A29DL163TV-70UF

更新时间: 2024-02-13 22:04:26
品牌 Logo 应用领域
联笙电子 - AMICC 闪存存储内存集成电路光电二极管
页数 文件大小 规格书
47页 738K
描述
Flash, 1MX16, 70ns, PDSO48

A29DL163TV-70UF 技术参数

是否Rohs认证:符合生命周期:Contact Manufacturer
包装说明:TSSOP, TSSOP48,.8,20Reach Compliance Code:unknown
风险等级:5.8Is Samacsys:N
最长访问时间:70 ns备用内存宽度:8
启动块:TOP命令用户界面:YES
通用闪存接口:YES数据轮询:YES
JESD-30 代码:R-PDSO-G48内存密度:16777216 bit
内存集成电路类型:FLASH内存宽度:16
部门数/规模:8,31端子数量:48
字数:1048576 words字数代码:1000000
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX16封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.8,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:PARALLEL电源:3/3.3 V
认证状态:Not Qualified就绪/忙碌:YES
部门规模:8K,64K最大待机电流:0.000005 A
子类别:Flash Memories最大压摆率:0.045 mA
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
切换位:YES类型:NOR TYPE
Base Number Matches:1

A29DL163TV-70UF 数据手册

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A29DL16x Series  
The  
pin may be tied to the system reset circuitry. A  
RESET  
sleep mode is independent of the  
,
and  
control  
OE  
WE  
CE  
system reset would thus also reset the Flash memory,  
enabling the system to read the boot-up firmware from the  
Flash memory.  
signals. Standard address access timings provide new data  
when addresses are changed. While in sleep mode, output  
data is latched and always available to the system. ICC4 in the  
DC Characteristics table represents the automatic sleep  
mode current specification.  
If  
is asserted during a program or erase operation,  
RESET  
the RY/  
pin remains a “0” (busy) until the internal reset  
BY  
operation is complete, which requires a time tREADY (during  
Embedded Algorithms). The system can thus monitor  
: Hardware Reset Pin  
RESET  
The  
pin provides a hardware method of resetting  
RY/  
BY  
complete. If  
to determine whether the reset operation is  
RESET  
the device to reading array data. When the system drives the  
is asserted when a program or erase  
RESET  
pin low for at least a period of tRP, the device  
immediately terminates any operation in progress, tristates  
all data output pins, and ignores all read/write attempts for  
RESET  
operation is not executing (RY/  
operation is completed within a time of tREADY (not during  
Embedded Algorithms). The system can read data tRH after  
pin is “1”), the reset  
BY  
the duration of the  
pulse. The device also resets the  
RESET  
the  
pin return to VIH.  
RESET  
internal state machine to reading array data. The operation  
that was interrupted should be reinitiated once the device is  
ready to accept another command sequence, to ensure data  
integrity.  
Refer to the AC Characteristics tables for  
parameters and diagram.  
RESET  
Output Disable Mode  
Current is reduced for the duration of the  
pulse.  
RESET  
When the  
input is at VIH, output from the device is  
OE  
When  
is held at VSS ± 0.3V, the device draws  
RESET  
disabled. The output pins are placed in the high impedance  
state.  
CMOS standby current (ICC4 ). If  
is held at VIL but not  
RESET  
within VSS ± 0.3V, the standby current will be greater.  
Table 2. A29DL16x Device Bank Divisions  
Device  
Part Number  
Bank 1  
Sector Sizes  
Bank 2  
Sector Sizes  
Megabits  
Megabits  
Eight 8 Kbyte/4 Kword,  
three 64 Kbyte/32 Kword  
Twenty-eight  
64 Kbyte/32 Kword  
A29DL162  
2 Mbit  
14 Mbit  
Eight 8 Kbyte/4 Kword,  
seven 64 Kbyte/32 Kword  
Twenty-four  
64 Kbyte/32 Kword  
A29DL163  
A29DL164  
4 Mbit  
8 Mbit  
12 Mbit  
8 Mbit  
Eight 8 Kbyte/4 Kword,  
fifteen 64 Kbyte/32 Kword  
Sixteen  
64 Kbyte/32 Kword  
PRELIMINARY (September, 2004, Version 0.0)  
7
AMIC Technology, Corp.  

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