Datasheet > A29002UL-150

A29002UL-150

更新时间： 2024-02-11 03:15:51

品牌	Logo	应用领域
联笙电子 - AMICC		闪存
页数	文件大小	规格书
32页	314K
描述
256K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory

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A29002UL-150 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
零件包装代码：	QFJ	包装说明：	LEAD FREE, PLASTIC, LCC-32
针数：	32	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.51
风险等级：	5.56	最长访问时间：	150 ns
其他特性：	BOTTOM BOOT SECTOR	启动块：	BOTTOM
命令用户界面：	YES	数据轮询：	YES
耐久性：	100000 Write/Erase Cycles	JESD-30 代码：	R-PQCC-J32
长度：	13.97 mm	内存密度：	2097152 bit
内存集成电路类型：	FLASH	内存宽度：	8
功能数量：	1	部门数/规模：	1,2,1,3
端子数量：	32	字数：	262144 words
字数代码：	256000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC32,.5X.6
封装形状：	RECTANGULAR	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	电源：	5 V
编程电压：	5 V	认证状态：	Not Qualified
座面最大高度：	3.4 mm	部门规模：	16K,8K,32K,64K
最大待机电流：	0.000005 A	子类别：	Flash Memories
最大压摆率：	0.04 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
切换位：	YES	类型：	NOR TYPE
宽度：	11.43 mm	Base Number Matches：	1

A29002UL-150 数据手册

A29002/A290021 Series

Any commands written to the chip during the Embedded

Erase algorithm are ignored. The system can determine the

status of the erase operation by using I/O7, I/O6, or I/O2. See

"Write Operation Status" for information on these status bits.

When the Embedded Erase algorithm is complete, the device

returns to reading array data and addresses are no longer

latched.

Figure 3 illustrates the algorithm for the erase operation. See

the Erase/Program Operations tables in "AC Characteristics"

for parameters, and to the Chip/Sector Erase Operation

Timings for timing waveforms.

START

Write Program

Command

Sequence

Sector Erase Command Sequence

Data Poll

from System

Embedded

Program

algorithm in

progress

Sector erase is a six-bus-cycle operation. The sector erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the address of the sector to be

erased, and the sector erase command. The Command

Definitions table shows the address and data requirements

for the sector erase command sequence.

The device does not require the system to preprogram the

memory prior to erase. The Embedded Erase algorithm

automatically programs and verifies the sector for an all zero

data pattern prior to electrical erase. The system is not

required to provide any controls or timings during these

operations.

After the command sequence is written, a sector erase time-

out of 50ms begins. During the time-out period, additional

sector addresses and sector erase commands may be

written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one

sector to all sectors. The time between these additional

cycles must be less than 50ms, otherwise the last address

and command might not be accepted, and erasure may

begin. It is recommended that processor interrupts be

disabled during this time to ensure all commands are

accepted. The interrupts can be re-enabled after the last

Sector Erase command is written. If the time between

additional sector erase commands can be assumed to be

less than 50ms, the system need not monitor I/O3. Any

command other than Sector Erase or Erase Suspend during

the time-out period resets the device to reading array data.

The system must rewrite the command sequence and any

additional sector addresses and commands.

Verify Data ?

Yes

Increment Address

Last Address ?

Yes

Programming

Completed

Note : See the appropriate Command Definitions table for

program command sequence.

Figure 2. Program Operation

Chip Erase Command Sequence

The system can monitor I/O3 to determine if the sector erase

timer has timed out. (See the " I/O3: Sector Erase Timer"

section.) The time-out begins from the rising edge of the final

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the chip erase command, which

in turn invokes the Embedded Erase algorithm. The device

does not require the system to preprogram prior to erase.

The Embedded Erase algorithm automatically preprograms

and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to provide

any controls or timings during these operations. The

Command Definitions table shows the address and data

requirements for the chip erase command sequence.

pulse in the command sequence.

Once the sector erase operation has begun, only the Erase

Suspend command is valid. All other commands are ignored.

When the Embedded Erase algorithm is complete, the device

returns to reading array data and addresses are no longer

latched. The system can determine the status of the erase

operation by using I/O7, I/O6, or I/O2. Refer to "Write

Operation Status" for information on these status bits.

(February, 2002, Version 1.0)

AMIC Technology, Inc.

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与A29002UL-150相关器件

型号	品牌	描述	获取价格	数据表
A29002UL-150F	AMICC	Flash, 256KX8, 150ns, PQCC32, LEAD FREE, PLASTIC, LCC-32	获取价格
A29002UL-55	AMICC	256K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格
A29002UL-55F	AMICC	Flash, 256KX8, 55ns, PQCC32, LCC-32	获取价格
A29002UL-70	AMICC	256K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格
A29002UL-70F	AMICC	Flash, 256KX8, 70ns, PQCC32, LEAD FREE, PLASTIC, LCC-32	获取价格
A29002UL-90	AMICC	256K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory	获取价格

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