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A25L80PQ-F PDF预览

A25L80PQ-F

更新时间： 2024-02-13 22:27:36
品牌 Logo 应用领域
联笙电子 - AMICC 时钟光电二极管内存集成电路
页数 文件大小 规格书
37页 462K
描述
Flash, 1MX8, PDSO8, QFN-8

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A25L80PQ-F 技术参数

是否Rohs认证： 符合生命周期：Contact Manufacturer
包装说明：HVSON, SOLCC8,.25Reach Compliance Code：unknown
风险等级：5.69其他特性：IT ALSO OPERATES AT FREQUENCY 50 MHZ AT 2.7 TO 3.6 V SUPPLY VOLTAGE
最大时钟频率 (fCLK)：75 MHz数据保留时间-最小值：20
耐久性：100000 Write/Erase CyclesJESD-30 代码：R-PDSO-N8
长度：6 mm内存密度：8388608 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1端子数量：8
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：1MX8
封装主体材料：PLASTIC/EPOXY封装代码：HVSON
封装等效代码：SOLCC8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE并行/串行：SERIAL
电源：3/3.3 V编程电压：2.7 V
认证状态：Not Qualified座面最大高度：0.8 mm
串行总线类型：SPI最大待机电流：0.00001 A
子类别：Flash Memories最大压摆率：0.015 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：NO LEAD端子节距：1.27 mm
端子位置：DUAL类型：NOR TYPE
宽度：5 mm写保护：HARDWARE/SOFTWARE
Base Number Matches：1

A25L80PQ-F 数据手册

 浏览型号A25L80PQ-F的Datasheet PDF文件第4页浏览型号A25L80PQ-F的Datasheet PDF文件第5页浏览型号A25L80PQ-F的Datasheet PDF文件第6页浏览型号A25L80PQ-F的Datasheet PDF文件第8页浏览型号A25L80PQ-F的Datasheet PDF文件第9页浏览型号A25L80PQ-F的Datasheet PDF文件第10页 
A25L80P Series  
Table 1. Protected Area Sizes  
Status Register Content  
Memory Content  
BP2 Bit  
BP1 Bit  
BP0 Bit  
Protected Area  
Unprotected Area  
0
1
0
1
0
1
none  
All sectors (sixteen sectors: 0 to 15)  
All sectors1 (sixteen sectors: 0 to 15)  
none  
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.  
2. The sector 0 include sector 0-0, sector 0-1, sector 0-2 and sector 0-3.  
Hold Condition  
with Serial Clock (C) being Low, the Hold condition ends  
after Serial Clock (C) next goes Low. This is shown in Figure  
3.  
During the Hold condition, the Serial Data Output (Q) is high  
impedance, and Serial Data Input (D) and Serial Clock (C)  
are Don’t Care.  
The Hold (  
) signal is used to pause any serial  
HOLD  
communications with the device without resetting the  
clocking sequence. However, taking this signal Low does not  
terminate any Write Status Register, Program or Erase cycle  
that is currently in progress.  
To enter the Hold condition, the device must be selected,  
Normally, the device is kept selected, with Chip Select (  
)
S
with Chip Select ( ) Low.  
S
The Hold condition starts on the falling edge of the Hold  
driven Low, for the whole duration of the Hold condition. This  
is to ensure that the state of the internal logic remains  
unchanged from the moment of entering the Hold condition.  
(
) signal, provided that this coincides with Serial Clock  
HOLD  
(C) being Low (as shown in Figure 3.).  
The Hold condition ends on the rising edge of the Hold  
If Chip Select ( ) goes High while the device is in the Hold  
S
condition, this has the effect of resetting the internal logic of  
the device. To restart communication with the device, it is  
(
) signal, provided that this coincides with Serial Clock  
HOLD  
(C) being Low.  
necessary to drive Hold (  
) High, and then to drive  
HOLD  
If the falling edge does not coincide with Serial Clock (C)  
being Low, the Hold condition starts after Serial Clock (C)  
next goes Low. Similarly, if the rising edge does not coincide  
Chip Select ( ) Low. This prevents the device from going  
S
back to the Hold condition.  
Figure 3. Hold Condition Activation  
C
HOLD  
Hold  
Hold  
Condition  
Condition  
(standard use)  
(non-standard use)  
(April, 2007, Version 1.5)  
6
AMIC Technology Corp.  
1...45678910...37

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