Datasheet > A1460

A1460

更新时间： 2022-05-06 10:10:10

品牌	Logo	应用领域
ACTEL		布线
页数	文件大小	规格书
98页	2009K
描述
Highly Predictable Performance with 100% Automatic Placement and Routing

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中文翻译

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数据手册

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A1460 数据手册

HiRel FPGAs

Actel Extended Flow¹

Require-

ment

Step Screen

Method

Wafer Lot Acceptance²

Destructive In-Line Bond Pull³

Internal Visual

5007 with Step Coverage Waiver

2011, Condition D

All Lots

Sample

100%

All Lots

2010, Condition A

Serialization

Temperature Cycling

Constant Acceleration

Particle Impact Noise Detection

Radiographic

1010, Condition C

2001, Condition D or E, Y₁Orientation Only

2020, Condition A

2012 (one view only)

Pre-Burn-In Test

In accordance with applicable Actel device specification

1015, Condition D, 240 hours @ 125°C minimum

10.

11.

12.

13.

Burn-in Test

Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification

Reverse Bias Burn-In 1015, Condition C, 72 hours @ 150°C minimum

Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification

Percent Defective Allowable (PDA)

Calculation

5%, 3% Functional Parameters @ 25°C

14.

15.

Final Electrical Test

In accordance with Actel applicable device specification

which includes a, b, and c:

100%

a. Static Tests

(1) 25°C

5005

(Subgroup 1, Table1)

(2) –55°C and +125°C

(Subgroups 2, 3, Table 1)

b. Functional Tests

100%

(1) 25°C

5005

(Subgroup 7, Table 15)

(2) –55°C and +125°C

(Subgroups 8A and B, Table 1)

c. Switching Tests at 25°C

(Subgroup 9, Table 1)

100%

5005

1014

16.

Seal

a. Fine

b. Gross

17.

External Visual

2009

100%

Notes:

1. Actel offers the extended flow for customers who require additional screening beyond the requirements of the MIL-STD-833, Class B. Actel is

compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flow

incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. The exceptions to Method 5004

are shown in notes 2 and 3 below.

2. Wafer lot acceptance is performed to Method 5007; however, the step coverage requirement as specified in Method 2018 must be waived.

3. MIL-STD-883, Method 5004 requires 100 percent Radiation latch-up testing (Method 1020). Actel will not be performing any radiation testing,

and this requirement must be waived in its entirety.

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与A1460相关器件

型号	品牌	获取价格	描述	数据表
A1460A	MICROSEMI	获取价格	Accelerator Series FPGAs â ACT 3 Family
A1460A-1BG225C	MICROSEMI	获取价格	Field Programmable Gate Array, 848 CLBs, 6000 Gates, 125MHz, CMOS, PBGA225, PLASTIC, BGA-2
A1460A-1BGG225C	MICROSEMI	获取价格	FPGA, 848 CLBS, 6000 GATES, 125MHz, PBGA225, ROHS COMPLIANT, PLASTIC, BGA-225
A1460A-1CQ196B	ACTEL	获取价格	HiRel FPGAs
A1460A-1CQ196C	ETC	获取价格	Field Programmable Gate Array (FPGA)
A1460A-1CQ196E	ACTEL	获取价格	Field Programmable Gate Array, 848 CLBs, 6000 Gates, 100MHz, CMOS, CQFP196, CAVITY-UP, CER
A1460A-1CQ196M	ACTEL	获取价格	Field Programmable Gate Array, 848 CLBs, 18000 Gates, 100MHz, 848-Cell, CMOS, CQFP196, CER
A1460A-1CQ256B	ACTEL	获取价格	HiRel FPGAs
A1460A-1CQ256C	ACTEL	获取价格	HiRel FPGAs
A1460A-1CQ256E	ACTEL	获取价格	HiRel FPGAs

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