Datasheet > A1425A-2PQ160C

A1425A-2PQ160C

更新时间： 2024-01-20 20:32:52

品牌	Logo	应用领域
美高森美 - MICROSEMI		/
页数	文件大小	规格书
90页	4491K
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A1425A-2PQ160C 数据手册

2 – Detailed Specifications

This section of the datasheet is meant to familiarize the user with the architecture of the ACT 3 family of

FPGA devices. A generic description of the family will be presented first, followed by a detailed

description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The

on-chip circuitry required to program the devices is not covered.

Topology

The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad

Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is

similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array

itself consists of alternating rows of modules and channels. The logic modules and channels are in the

center of the array; the I/O modules are located along the array periphery. A simplified floor plan is

depicted in Figure 2-1.

An Array with n rows and m columns

c–1

c+1

m m+1 m+2 m+3

Columns

Rows

n+1

Channels

n+2

IO IO IO IO IO IO

Top I/Os

IO IO IO CLKM

n+1

IO IO BIN S

IO IO

n–1

•

n–1

•

IO IO

IO IO BIN S

Left I/Os

Right I/Os

Bottom I/Os

BIO IO IO IO IO IO

IO IO IO IO IO IO

Figure 2-1 • Generalized Floor Plan of ACT 3 Device

Revision 3

2-1

1...6 7 8910 11 12...90

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