Datasheet > A14100BP-2BG313C

A14100BP-2BG313C

更新时间： 2022-12-02 00:53:48

品牌	Logo	应用领域
ACTEL		栅
页数	文件大小	规格书
40页	1250K
描述
Field Programmable Gate Array, 1377 CLBs, 10000 Gates, 150MHz, 1377-Cell, CMOS, PBGA313, PLASTIC, BGA-313

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A14100BP-2BG313C 数据手册

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Accelerator Series FPGAs: ACT 3 PCI-Compliant Family

the input of S-modules or I/O modules. There are two

dedicated clock networks: one for the array registers (HCLK),

and one for the I/O registers (IOCLK). The clock networks

are accessed by special I/Os.

SLEW

Routed Clocks

The routed clock networks are referred to as CLK0 and CLK1.

Each network is connected to a clock module (CLKMOD)

that selects the source of the clock signal, and may be driven

as follows (see Figure 6):

DATAOUT

•

Externally from the CLKA Pad

Externally from the CLKB Pad

Internally from the CLKINA Input

Internally from the CLKINB Input

PAD

DATAIN

IEN

The clock modules are located in the top row of the I/O

modules. Clock drivers and a dedicated horizontal clock track

are located in each horizontal routing channel. The function

of the clock module is determined by the selection of clock

macros from the macro library. The macro CLKBUF is used to

connect one of the two external clock pins to a clock network,

and the macro CLKINT is used to connect an internally

generated clock signal to a clock network. Since both clock

networks are identical, the user may use either CLK0 or

CLK1. Routed clocks can also be used to drive high-fanout

nets like resets, output enables, or data enables. This saves

logic modules and results in performance increases in some

cases.

INEN

OUTEN

Figure 5 • Function Diagram for I/O Pad Driver

Special I/Os

The special I/Os are of two types: temporary and permanent.

Temporary special I/Os are used during programming and

testing, and function as normal I/Os when the MODE pin is

inactive. Permanent special I/Os are user-programmed as

either normal I/Os or special I/Os. Their function does not

change once the device has been programmed. The

permanent special I/Os consist of the array clock input

buffers (CLKA and CLKB), the hard-wired array clock input

buffer (HCLK), the hard-wired I/O clock input buffer

(IOCLK), and the hard-wired I/O register preset/clear input

buffer (IOPCL). Their function is determined by the I/O

macros selected.

CLKB

CLKA

CLKINB

CLKINA

From

Pads

Internal

Signal

CLKMOD

CLKO(17)

CLKO(16)

CLKO(15)

Clock Networks

The ACT 3 architecture contains four clock networks: two

high-performance dedicated clock networks and two

general-purpose routed networks. The high-performance

networks function up to 200 MHz, while the general-purpose

routed networks function up to 150 MHz.

Clock

Drivers

CLKO(2)

CLKO(1)

Dedicated Clocks

Dedicated clock networks support high performance by

providing sub-nanosecond skew and predictable

performance. Dedicated clock networks contain no

programming elements in the path from the I/O pad driver to

Clock Tracks

Figure 6 • Clock Networks

1...4 5 678 9 10...40

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与A14100BP-2BG313C相关器件

型号	品牌	描述	获取价格	数据表
A14100BP-3RQ208I	ACTEL	Field Programmable Gate Array, 1377 CLBs, 10000 Gates, 200MHz, 1377-Cell, CMOS, PQFP208, H	获取价格
A14100BP-BG313C	ACTEL	Field Programmable Gate Array, 1377 CLBs, 10000 Gates, 100MHz, 1377-Cell, CMOS, PBGA313, P	获取价格
A14100B-RQ208C	MICROSEMI	Field Programmable Gate Array, 100MHz, 1377-Cell, CMOS, PQFP208	获取价格
A14100B-RQ208I	MICROSEMI	Field Programmable Gate Array, 93.5MHz, 1377-Cell, CMOS, PQFP208	获取价格
A14101000NS	RCD	Active Delay Line, 1-Func, 10-Tap, True Output, TTL, PDIP14, PLASTIC, DIP-14	获取价格
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