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A1410-150NS-B PDF预览

A1410-150NS-B

更新时间： 2024-02-23 22:34:10
品牌 Logo 应用领域
RCD 光电二极管逻辑集成电路延迟线
页数 文件大小 规格书
1页 84K
描述
Active Delay Line, 1-Func, 10-Tap, Hybrid, PDIP14, DIP-14

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A1410-150NS-B 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP14,.3针数：14
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.05JESD-30 代码：R-PDIP-P14
JESD-609代码：e0/e3逻辑集成电路类型：ACTIVE DELAY LINE
功能数量：1抽头/阶步数：10
端子数量：14最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP14,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
可编程延迟线：NOProp。Delay @ Nom-Sup：150 ns
认证状态：Not Qualified座面最大高度：7.62 mm
子类别：Delay Lines最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：HYBRID
温度等级：COMMERCIAL端子面层：TIN LEAD/MATTE TIN
端子形式：PIN/PEG端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总延迟标称（td）：150 ns宽度：7.62 mm
Base Number Matches：1

A1410-150NS-B 数据手册

  
ACTIVE (DIGITAL) DELAY LINES  
RESISTORS"CAPS&COILS"DELAYLINES  
A0805 SERIES 5-TAP 8-PIN DIP  
SA0805 SERIES 5-TAP 8-PIN SIP  
A1405 SERIES 5-TAP 8-PIN DIP  
A1410 SERIES 10-TAP 14-PIN DIP  
Wide selection of sizes!  
RCD’s digital delay lines have been designed to provide precise tap  
delays with all the necessary drive and pick-off circuitry. All inputs and  
outputs are schottky-type and require no additional components to achieve  
specified delays. Encapsulated/molded construction ensures full com-  
pliance to all applicable requirements of MIL-D-23859. Units are 100%  
inspected for solder joint integrity and electrical conformance.  
FEATURES  
! Economical cost, prompt delivery!  
! Wide varieties of values  
! Choice of 5 or 10 equally spaced taps  
! TTL and DTL compatible  
! Operating temperature: 0°C to 70°C  
! Excellent for applications requiring high  
delay stability, fast rise times and no jitter,  
such as memory boards, disk drives, and  
signal processing  
TEST CONDITIONS @25°C  
1) Delay measured at 1.5V on leading edge only with no loads on output.  
2) Rise time measured from 0.75V to 2.4V.  
3) Delay will inversely vary approximately 4% for every 5% change in supply voltage.  
4) Supply voltage (VCC) = 5.0±.25VDC  
5) Input test pulse: 3.2V, 2nS rise time, width>40% of total delay, pulse period to be a  
minimum of 3x the pulse width.  
Outputs  
TYPE A0805 (Available  
7
2 6 3  
5
.500 [12.7]  
Max.  
OPTIONS  
←
→
20nS to 500nS)  
8
! Non-standard delay times or tolerances  
! Non-symmetrical tap delays  
! Dynamic RAM timing delay  
! Fast logic TTL available  
! Faster rise times  
! ECL, H-CMOS, and low power designs  
available  
! Option T - Measurement at both leading  
and trailing edges  
! Option ER - Ceramic IC’s screened to MIL-  
STD-883, -55 to +125°C per MIL-D-83532  
! Option 39 - -40-+85°C op. temp.  
↑
VCC  
↑
↓
.250  
[6.35]  
Max.  
↑
.400  
[10.2]  
Max.  
.300  
1
[7.62]  
IN  
G
↓
.100  
[2.54]  
Typ.  
.018  
[.457]→ ←  
Typ.  
↓
R
→
←
4
.300  
[7.62]  
←
→
Outputs  
TYPE SA0805 (Available 20nS to 250nS)  
3
4 5 6  
7
←.810 [20.6] Max.  
→
1
.180  
[4.57]  
→
←
.340  
[8.64]  
Max.  
VCC  
Max.  
2
.150  
[3.81]  
Typ.  
IN  
G
R
8
.100  
[2.54]  
Typ.  
→ ← .010  
.018  
[.457]  
Typ.  
→
←
→ ←  
.020  
[.51]  
[.254]  
Delay Per Tap  
(nSec)  
Total  
Delay  
TYPE A1410  
(Available 50nS to 1000nS)  
TYPE A1405A  
Auto Insertable Molded  
(20nS to 1000nS)--  
TYPE A1405 - Economy  
(20nS to 1000nS)  
A0805  
SA080 A1410  
A1405  
←.800 [20.3] Max.  
→
↓
.280  
[7.11]  
Max.  
20  
25  
30  
40  
50  
4
5
6
*
*
*
*
5
.120  
also avail. in .165” profile  
.300  
[7.62]  
Max.  
↑
↓
[3.05]  
Min.  
←
.785 [19.9] Max.→  
↓
.25  
8
↓
↑
.150  
[3.81]  
Typ.  
↑
↓
10  
12  
15  
20  
25  
30  
35  
40  
50  
60  
70  
80  
90  
100  
150  
200  
[6.35]  
↑
→
←
60  
75  
6
.018  
[.457]  
Typ.  
→ ←  
→
←
→ ←  
.020±.003  
[.5±.076]  
.100  
[2.54]  
Typ.  
7.5  
10  
12.5  
15  
17.5  
20  
25  
30  
35  
40  
45  
50  
75  
100  
↑
.100  
[2.54]  
100  
125  
150  
175  
200  
250  
300  
350  
400  
450  
500  
750  
1000  
.600±.010  
[12.7±.254]  
←
→
.050 [1.27]  
.100  
←.800 [20.3] Max.  
→
[2.54]  
.050 [1.27]  
Typ.  
↓
.280  
[7.11]  
.300  
[7.62]  
←
→
→
←
→
↓
↑
↑
↓
.400 [10.2]  
Max.  
↑
↑
↓
.400  
[10.2]  
.300±.01  
[7.62±.254]  
↓
←
→
.300±.010  
[7.62±.254]  
↓
↑
↓
.300±.010  
[7.62±.254]  
13 3 12 4 11 5 10 6 9  
8 OUT  
.600±.010  
[12.7±.254]  
.800 [20.3] Max.  
12  
4
10  
6
8 OUT  
←
←
→
→
14  
VCC  
IN  
1
.010  
[.254]  
14  
1
VCC  
IN  
G
R
R
7
G
7
* Consult factory for availability.  
ELECTRICAL CHARACTERISTICS  
A1405  
- 100nS - B  
P/N DESIGNATION:  
Total Delay Tolerance ±5% or 2nS (whichever is greater)  
Tap Delay Tolerance ±5% or 2nS (whichever is greater)  
RCD Type  
Options: (leave blank if standard)  
ER, T, 39, or as assigned by RCD  
Insulation Resistance  
Dielectric Strength  
Rise Time  
1000MΩ min.  
100VDC  
Total Delay  
Packaging: B=bulk (standard)  
4nS max.  
RCD Components Inc., 520 E. Industrial Park Dr., Manchester, NH, USA 03109  
Tel: (603) 669-0054 Fax:(603) 669-5455 E-mail: sales@rcdcomponents.com www.rcdcomponents.com  
FA specifications subject to change without notice  
1

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