Datasheet > A14100BP-2BG313C

A14100BP-2BG313C

更新时间： 2022-12-02 00:53:48

品牌	Logo	应用领域
ACTEL		栅
页数	文件大小	规格书
40页	1250K
描述
Field Programmable Gate Array, 1377 CLBs, 10000 Gates, 150MHz, 1377-Cell, CMOS, PBGA313, PLASTIC, BGA-313

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A14100BP-2BG313C 数据手册

Accelerator Series FPGAs: ACT 3 PCI-Compliant Family

An Array with n Rows and m Columns

c–1

c+1

m m+1 m+2 m+3

Columns

Rows

n+1

Channels

n+2

IO IO IO IO IO IO

Top I/Os

IO IO IO CLKM

n+1

IO IO BIN S

IO IO

n–1

•

n–1

•

IO IO

IO IO BIN S

Left I/Os

Right I/Os

Bottom I/Os

BIO IO IO IO IO IO

IO IO IO IO IO IO

Figure 1 • Generalized Floor Plan of ACT 3 Device

The I/O module output Y is used to bring pad signals into the

array or to feed the output register back into the array. This

allows the output register to be used in high-speed state

machine applications. Side I/O modules have a dedicated

output segment for Y extending into the routing channels

above and below (similar to logic modules). Top/Bottom I/O

modules have no dedicated output segment. Signals coming

into the chip from the top or bottom are routed using F-fuses

and LVTs (F-fuses and LVTs are explained in detail in the

routing section).

D00

D01

OUT

D10

D11

I/O Pad Drivers

All pad drivers are capable of being tri-state. Each buffer

connects to an associated I/O module with four signals: OE

(Output Enable), IE (Input Enable), DataOut, and DataIn.

Special signals used only during programming and test also

connect to the pad drivers: OUTEN (global output enable),

INEN (global input enable), and SLEW (individual slew

selection). See Figure 5.

A1 B1

A0 B0

Figure 2 • C-Module Diagram

preset/clear network (IOPCL). Either preset or clear can be

selected individually on an I/O-module-by-I/O-module basis.

1 2 3 456 7 8...40

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