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A14100A-1PGG257M PDF预览

A14100A-1PGG257M

更新时间： 2024-01-03 21:05:56
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟栅现场可编程门阵列可编程逻辑
页数 文件大小 规格书
90页 4491K
描述
Field Programmable Gate Array, 1377 CLBs, 10000 Gates, 125MHz, CMOS, CPGA257, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, PGA-257

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A14100A-1PGG257M 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：PLASTIC, BGA-313Reach Compliance Code：compliant
风险等级：5.83其他特性：MAX 228 I/OS
最大时钟频率：100 MHzCLB-Max的组合延迟：3 ns
JESD-30 代码：S-PBGA-B313JESD-609代码：e1
长度：35 mm湿度敏感等级：3
可配置逻辑块数量：1377等效关口数量：10000
端子数量：313最高工作温度：70 °C
最低工作温度：组织：1377 CLBS, 10000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：IBGA
封装形状：SQUARE封装形式：GRID ARRAY, INTERSTITIAL PITCH
峰值回流温度（摄氏度）：245可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：2.52 mm
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：2.54 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：35 mm
Base Number Matches：1

A14100A-1PGG257M 数据手册

 浏览型号A14100A-1PGG257M的Datasheet PDF文件第6页浏览型号A14100A-1PGG257M的Datasheet PDF文件第7页浏览型号A14100A-1PGG257M的Datasheet PDF文件第8页浏览型号A14100A-1PGG257M的Datasheet PDF文件第10页浏览型号A14100A-1PGG257M的Datasheet PDF文件第11页浏览型号A14100A-1PGG257M的Datasheet PDF文件第12页 
2 – Detailed Specifications  
This section of the datasheet is meant to familiarize the user with the architecture of the ACT 3 family of  
FPGA devices. A generic description of the family will be presented first, followed by a detailed  
description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The  
on-chip circuitry required to program the devices is not covered.  
Topology  
The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad  
Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is  
similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array  
itself consists of alternating rows of modules and channels. The logic modules and channels are in the  
center of the array; the I/O modules are located along the array periphery. A simplified floor plan is  
depicted in Figure 2-1.  
An Array with n rows and m columns  
0
1
2
3
4
5
c–1  
c
c+1  
m m+1 m+2 m+3  
Columns  
Rows  
n+1  
Channels  
n+2  
IO IO IO IO IO IO  
Top I/Os  
IO IO IO CLKM  
n+1  
n
IO IO BIN S  
IO IO BIN S  
IO IO BIN S  
S
S
S
S
C
C
C
C
C
C
C
C
S
S
S
S
S
S
S
S
C
C
C
C
C
C
C
C
S
S
S
S
C
C
C
C
S
S
S
S
IO IO  
n
IO IO  
IO IO  
n–1  
•
•
•
n–1  
•
•
•
2
2
IO IO  
IO IO BIN S  
Left I/Os  
1
0
1
0
Right I/Os  
Bottom I/Os  
BIO IO IO IO IO IO  
IO IO IO IO IO IO  
Figure 2-1 • Generalized Floor Plan of ACT 3 Device  
Revision 3  
2-1  
1...6789101112...90

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