Datasheet > A1240XLV-1PLB

A1240XLV-1PLB

更新时间： 2022-12-26 18:24:25

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
84页	3116K
描述
Integrator Series FPGAs: 1200XL and 3200DX Families

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中文翻译

获取价格

数据手册

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A1240XLV-1PLB 数据手册

Integrator Series FPGAs: 1200XL and 3200DX Families

QCLKA

QCLKC

Quad

Clock

Module

Quad

Clock

Module

QCLK1

QCLK3

QCLKB

QCLKD

*QCLK1IN

*QCLK3IN

S0 S1

S1 S0

Quad

Clock

Quad

Clock

QCLK2

QCLK4

Module

*QCLK2IN

*QCLK4IN

S0 S1

S1 S0

*QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.

Figure 8 • Quadrant Clock Network

JPROBE Register

Boundary Scan Register

Output

MUX

TDO

Bypass

Control Logic

JTAG

TMS

Instruction

Decode

TAP Controller

TCK

JTAG

Instruction

TDI

Figure 9 • 3200DX IEEE 1149.1 Boundary Scan Circuitry

Discontinued – v3.0

1...7 8 91011 12 13...84

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