5秒后页面跳转
捷配首页

Datasheet > A1020B-2PLG68C
A1020B-2PLG68C PDF预览

A1020B-2PLG68C

更新时间： 2024-02-01 09:24:51
品牌 Logo 应用领域
ACTEL 时钟栅可编程逻辑
页数 文件大小 规格书
24页 163K
描述
Field Programmable Gate Array, 547 CLBs, 2000 Gates, 60MHz, 547-Cell, CMOS, PQCC68, PLASTIC, MS-007-AD, LCC-68

阅读下载

获取价格

A1020B-2PLG68C 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：PLASTIC, MS-007-AD, LCC-68Reach Compliance Code：compliant
风险等级：5.77其他特性：MAX 57 I/OS
最大时钟频率：60 MHzCLB-Max的组合延迟：3.4 ns
JESD-30 代码：S-PQCC-J68JESD-609代码：e3
长度：24.13 mm湿度敏感等级：3
可配置逻辑块数量：547等效关口数量：2000
输入次数：69逻辑单元数量：547
输出次数：69端子数量：68
最高工作温度：70 °C最低工作温度：
组织：547 CLBS, 2000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC68,1.0SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：245电源：5 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：4.445 mm子类别：Field Programmable Gate Arrays
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：24.13 mm

A1020B-2PLG68C 数据手册

 浏览型号A1020B-2PLG68C的Datasheet PDF文件第5页浏览型号A1020B-2PLG68C的Datasheet PDF文件第6页浏览型号A1020B-2PLG68C的Datasheet PDF文件第7页浏览型号A1020B-2PLG68C的Datasheet PDF文件第9页浏览型号A1020B-2PLG68C的Datasheet PDF文件第10页浏览型号A1020B-2PLG68C的Datasheet PDF文件第11页 
E q u iv a le n t C a p a c it a n c e  
CEQM = Equivalent capacitance of logic modules in pF  
CEQI = Equivalent capacitance of input buffers in pF  
The power dissipated by a CMOS circuit can be expressed by  
the Equation 1.  
CEQO = Equivalent capacitance of output buffers in pF  
Power (uW) = CEQ * VCC2 * F  
(1)  
CEQCR = Equivalent capacitance of routed array clock in  
pF  
Where:  
CEQ is the equivalent capacitance expressed in pF.  
CL  
fm  
fn  
= Output lead capacitance in pF  
V is the power supply in volts.  
= Average logic module switching rate in MHz  
= Average input buffer switching rate in MHz  
= Average output buffer switching rate in MHz  
CC  
F is the switching frequency in MHz.  
Equivalent capacitance is calculated by measuring ICCactive  
at a specified frequency and voltage for each circuit  
component of interest. Measurements have been made over a  
fp  
fq1  
= Average first routed array clock rate in MHz (All  
families)  
range of frequencies at a fixed value of V . Equivalent  
CC  
capacitance is frequency independent so that the results may  
be used over a wide range of operating conditions. Equivalent  
capacitance values are shown below.  
F ix e d C a p a c it a n c e Va lu e s fo r Ac t e l F P G As  
(p F )  
r1  
C
Va lu e s fo r Ac t e l F P G As  
E Q  
Device Type  
A1010B  
routed_Clk1  
41.4  
68.6  
40  
A10V10B  
A10V20B  
A1010B  
A1020B  
A1020B  
Modules (CEQM  
Input Buffers (CEQI  
Output Buffers (CEQO  
Routed Array Clock Buffer  
Loads (CEQCR  
)
3.2  
10.9  
11.6  
3.7  
22.1  
31.2  
A10V10B  
A10V20B  
)
65  
)
De t e r m in in g Av e r a g e S w it c h in g F r e q u e n c y  
To determine the switching frequency for a design, you must  
have a detailed understanding of the data input values to the  
circuit. The following guidelines are meant to represent  
worst-case scenarios so that they can be generally used to  
predict the upper limits of power dissipation. These  
guidelines are as follows:  
)
4.1  
4.6  
To calculate the active power dissipated from the complete  
design, the switching frequency of each part of the logic must  
be known. Equation 2 shows a piece-wise linear summation  
over all components.  
Logic Modules (m)  
90% of modules  
#inputs/4  
Power = V 2 * [(m * CEQM * fm)modules  
+
CC  
Inputs switching (n)  
(n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs  
0.5 * (q1 * CEQCR * fq1)routed_Clk1  
(r1 * fq1)routed_Clk1  
+
Outputs switching (p)  
First routed array clock loads (q1)  
Load capacitance (CL)  
#outputs/4  
40% of modules  
35 pF  
+
]
(2)  
Where:  
Average logic module switching rate (fm) F/10  
m
n
= Number of logic modules switching at fm  
= Number of input buffers switching at fn  
= Number of output buffers switching at fp  
Average input switching rate (fn)  
Average output switching rate (fp)  
F/5  
F/10  
p
Average first routed array clock rate F  
(fq1)  
q1  
= Number of clock loads on the first routed array  
clock (All families)  
r1  
= Fixed capacitance due to first routed array  
clock (All families)  
1 -2 9 0  
1...567891011...24

下载PDF

与A1020B-2PLG68C相关器件

型号 品牌 描述 获取价格 数据表
A1020B-2PLG68I ACTEL Field Programmable Gate Array, 547 CLBs, 2000 Gates, 54.1MHz, 547-Cell, CMOS, PQCC68, PLAS

获取价格
A1020B-2PLG84C ACTEL Field Programmable Gate Array, 547 CLBs, 2000 Gates, 60MHz, 547-Cell, CMOS, PQCC84, PLASTI

获取价格
A1020B-2PLG84I ACTEL Field Programmable Gate Array, 547 CLBs, 2000 Gates, 54.1MHz, 547-Cell, CMOS, PQCC84, PLAS

获取价格
A1020B-2PQ100C MICROSEMI Field Programmable Gate Array, 547 CLBs, 2000 Gates, 60MHz, 547-Cell, CMOS, PQFP100, PLAST

获取价格
A1020B-2PQ100I ACTEL Field Programmable Gate Array, 547 CLBs, 2000 Gates, 54.1MHz, 547-Cell, CMOS, PQFP100, PLA

获取价格
A1020B-2PQ100I MICROSEMI Field Programmable Gate Array, 547 CLBs, 2000 Gates, 54.1MHz, 547-Cell, CMOS, PQFP100, PLA

获取价格

与A1020B-2PLG68C相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证