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74HCT4052PW

更新时间： 2024-01-01 02:14:17
品牌 Logo 应用领域
恩智浦 - NXP 解复用器开关复用器或开关信号电路光电二极管
页数 文件大小 规格书
27页 277K
描述
Dual 4-channel analog multiplexer/demultiplexer

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74HCT4052PW 技术参数

生命周期：Obsolete包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.47模拟集成电路 - 其他类型：DIFFERENTIAL MULTIPLEXER
JESD-30 代码：R-PDSO-G16标称负供电电压 (Vsup)：
信道数量：4功能数量：1
端子数量：16标称断态隔离度：50 dB
通态电阻匹配规范：9 Ω最大通态电阻 (Ron)：180 Ω
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
认证状态：Not Qualified标称供电电压 (Vsup)：4.5 V
表面贴装：YES最长断开时间：50 ns
最长接通时间：70 ns技术：CMOS
温度等级：AUTOMOTIVE端子形式：GULL WING
端子位置：DUALBase Number Matches：1

74HCT4052PW 数据手册

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74HC4052; 74HCT4052  
Dual 4-channel analog multiplexer/demultiplexer  
Rev. 06 — 11 January 2010  
Product data sheet  
1. General description  
The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible  
with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A.  
The 74HC4052; 74HCT4052 is a dual 4-channel analog multiplexer/demultiplexer with  
common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to  
nY3) and a common input/output (pin nZ). The common channel select logics include two  
digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When  
pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0  
and S1. When pin E = HIGH, all switches are in the high-impedance OFF-state,  
independent of pins S0 and S1.  
VCC and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E).  
The VCC to GND ranges are 2.0 V to 10.0 V for the 74HC4052 and 4.5 V to 5.5 V for the  
74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between VCC  
as a positive limit and VEE as a negative limit. VCC − VEE may not exceed 10.0 V.  
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically  
ground).  
2. Features  
„ Wide analog input voltage range from −5 V to +5 V  
„ Low ON resistance:  
‹ 80 Ω (typical) at VCC − VEE = 4.5 V  
‹ 70 Ω (typical) at VCC − VEE = 6.0 V  
‹ 60 Ω (typical) at VCC − VEE = 9.0 V  
„ Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals  
„ Typical ‘break before make’ built-in  
„ Complies with JEDEC standard no. 7A  
„ ESD protection:  
‹ HBM JESD22-A114F exceeds 2000 V  
‹ MM JESD22-A115-A exceeds 200 V  
„ Specified from −40 °C to +85 °C and −40 °C to +125 °C  
3. Applications  
„ Analog multiplexing and demultiplexing  
„ Digital multiplexing and demultiplexing  
„ Signal gating  
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