5秒后页面跳转
74VHC161284MEAX PDF预览

74VHC161284MEAX

更新时间: 2024-01-12 10:41:40
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
12页 212K
描述
IEEE 1284 Transceiver

74VHC161284MEAX 数据手册

 浏览型号74VHC161284MEAX的Datasheet PDF文件第2页浏览型号74VHC161284MEAX的Datasheet PDF文件第3页浏览型号74VHC161284MEAX的Datasheet PDF文件第4页浏览型号74VHC161284MEAX的Datasheet PDF文件第5页浏览型号74VHC161284MEAX的Datasheet PDF文件第6页浏览型号74VHC161284MEAX的Datasheet PDF文件第7页 
February 1998  
Revised June 2005  
74VHC161284  
IEEE 1284 Transceiver  
General Description  
Features  
Supports IEEE 1284 Level 1 and Level 2 signaling  
standards for bidirectional parallel communications  
between personal computers and printing peripherals  
The VHC161284 contains eight bidirectional data buffers  
and eleven control/status buffers to implement  
a full  
IEEE 1284 compliant interface. The device supports the  
IEEE 1284 standard and is intended to be used in  
Extended Capabilities Port mode (ECP). The pinout allows  
for easy connection from the Peripheral (A-side) to the  
Host (cable side).  
Replaces the function of two (2) 74ACT1284 devices  
All inputs have hysteresis to provide noise margin  
B and Y output resistance optimized to drive external  
cable  
Outputs on the cable side can be configured to be either  
open drain or high drive ( 14 mA). The pull-up and pull-  
down series termination resistance of these outputs on the  
cable side is optimized to drive an external cable. In addi-  
tion, all inputs (except HLH) and outputs on the cable side  
contain internal pull-up resistors connected to the VCC sup-  
B and Y outputs in high impedance mode during power  
down  
Inputs and outputs on cable side have internal pull-up  
resistors  
Flow-through pin configuration allows easy interface  
ply to provide proper termination and pull-ups for open  
drain mode.  
between the Peripheral and Host  
Outputs on the Peripheral side are standard LOW-drive  
CMOS outputs. The DIR input controls data flow on the A1–  
A8/B1–B8 transceiver pins.  
Ordering Code:  
Ordering Number Package Number  
Package Description  
74VHC161284MEA  
74VHC161284MTD  
MS48A  
MTD48  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter Xto the ordering code.  
Logic Symbol  
Connection Diagram  
© 2005 Fairchild Semiconductor Corporation  
DS500098  
www.fairchildsemi.com  

与74VHC161284MEAX相关器件

型号 品牌 描述 获取价格 数据表
74VHC161284MEAX_NL FAIRCHILD Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 0.300 INCH, MO-118, SSOP-48

获取价格

74VHC161284MTD FAIRCHILD IEEE 1284 Transceiver

获取价格

74VHC161284MTDX FAIRCHILD IEEE 1284 Transceiver

获取价格

74VHC161284MTDX ONSEMI IEEE 161284收发器

获取价格

74VHC161284MTDX_NL FAIRCHILD Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48

获取价格

74VHC161FT TOSHIBA 4-bit Binary Counter, TSSOP16B

获取价格