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74VHC16373 PDF预览

74VHC16373

更新时间: 2024-11-16 04:48:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器输出元件
页数 文件大小 规格书
11页 283K
描述
16-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING

74VHC16373 数据手册

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74VHC16373  
16-BIT D-TYPE LATCH  
WITH 3-STATE OUTPUTS NON INVERTING  
HIGH SPEED:  
= 5.0 ns (TYP.) at V = 5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4 µA (MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
TSSOP  
TUBE  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
T & R  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
TSSOP  
74VHC16373TTR  
V
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 16373  
PIN CONNECTION  
IMPROVED LATCH-UP IMMUNITY  
LOW NOISE: V  
= 0.9V (MAX.)  
OLP  
DESCRIPTION  
The 74VHC16373 is an advanced high-speed  
CMOS 16 BIT D-TYPE LATCH with 3 STATE  
OUTPUTS NON INVERTING fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology.  
These 16 bit D-TYPE latches are byte controlled  
by two latch enable inputs (nLE) and two output  
enable inputs(nOE).  
While the nLE input is held at a high level, the nQ  
outputs will follow the data (D) inputs.  
When the nLE is taken LOW, the nQ outputs will  
be latched at the logic level of D data inputs.  
When the (nOE) input is low, the nQ outputs will  
be in a normal logic state (high or low logic level);  
when nOE is at high level ,the outputs will be in a  
high impedance state.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
All inputs and outputs are equipped with protec-  
tion circuits against static discharge, giving them  
2KV ESD immunity and transient excess voltage.  
February 2003  
1/11  

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