5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > 其他 uPs/uCs/外围集成电路> 9LPRS535CGLF
9LPRS535CGLF PDF预览

9LPRS535CGLF

更新时间： 2024-01-07 01:27:12
品牌 Logo 应用领域
艾迪悌 - IDT 微控制器和处理器外围集成电路uCs集成电路uPs集成电路光电二极管
页数 文件大小 规格书
17页 221K
描述
48-pin CK505 for Intel Systems

阅读下载

获取价格

9LPRS535CGLF 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
针数：48Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.84JESD-30 代码：R-PDSO-G48
长度：12.5 mm端子数量：48
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：6.1 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT

9LPRS535CGLF 数据手册

 浏览型号9LPRS535CGLF的Datasheet PDF文件第1页浏览型号9LPRS535CGLF的Datasheet PDF文件第2页浏览型号9LPRS535CGLF的Datasheet PDF文件第4页浏览型号9LPRS535CGLF的Datasheet PDF文件第5页浏览型号9LPRS535CGLF的Datasheet PDF文件第6页浏览型号9LPRS535CGLF的Datasheet PDF文件第7页 
Integrated  
Circuit  
Systems, Inc.  
ICS9LPRS535  
Datasheet  
SSOP/TSSOP Pin Description (Continued)  
Stops all PCICLKs at logic 0 level, when low. Can also stop SRC clocks. Free running PCICLKs are not effected by this  
input. / True clock of push-pull SRC pair with int. 33ohm series resistor.  
25 PCI_STOP#/SRCT5_LPR  
I/O  
26 VDDSRC  
27 GNDSRC  
PWR Supply for SRC clocks, 3.3V nominal  
PWR Ground pin for the SRC outputs  
Complementary clock of push-pull SRC output with int. 33ohm series resistor/CR#_E input. Disable SRC7 via Byte 3, bit 3  
before using as CR#_E.  
Byte 6, bit 7: 0=SRC7 (default), 1=CR#_E  
28 SRCC7_LPR/CR#_E  
I/O  
Outputs controlled by CR#_E are not present on this device  
True clock of push-pull SRC output with int. 33 ohm series resistor/CR#_F input. Disable SRC7 via Byte 3, bit 3 before  
I/O using CR#_F.  
Byte 6, bit 6: 0 = SRC7 (default),1 = CR#_F enabled to control SRC8.  
PWR 1.05V to 3.3V from external power supply  
29 SRCT7_LPR/CR#_F  
30 VDDSRC_IO  
Complementary clock of low power differential CPU2_ITP/SRC pair. No Rs needed. The function of this pin is determined  
by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:  
31 CPUC2_ITP_LPR/SRCC8_LPR OUT Pin 7 latched input Value  
0 = SRC8#  
1 = ITP#  
True clock of low power differential CPU2_ITP/SRC8 pair. No Rs needed. The function of this pin is determined by the  
latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:  
32 CPUT2_ITP_LPR/SRCT8_LPR OUT Pin 7 latched input Value  
0 = SRC8  
1 = ITP  
33 VDDCPU_IO  
PWR 1.05V to 3.3V from external power supply  
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running  
during iAMT. No 50ohm resistor to GND needed.  
34 CPUC1_LPR_F  
OUT  
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running during  
iAMT No 50 ohm resistor to GND needed.  
PWR Ground pin for the CPU outputs  
35 CPUT1_LPR_F  
36 GNDCPU  
OUT  
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm  
resistor to GND needed.  
37 CPUC0_LPR  
OUT  
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm resistor to  
GND needed.  
38 CPUT0_LPR  
OUT  
39 VDDCPU  
PWR Supply for CPU clocks, 3.3V nominal  
40 CK_PWRGD/PD#  
IN Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode  
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.  
IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test  
Clarification Table.  
41 FSLB/TEST_MODE  
42 GNDREF  
43 X2  
PWR Ground pin for the REF outputs.  
OUT Crystal output, Nominally 14.318MHz  
IN Crystal input, Nominally 14.318MHz.  
PWR Ref, XTAL power supply, nominal 3.3V  
44 X1  
45 VDDREF  
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for  
Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table  
46 REF0/FSLC/TEST_SEL  
I/O  
47 SDATA  
48 SCLK  
I/O Data pin for SMBus circuitry, 3.3V tolerant.  
IN Clock pin of SMBus circuitry, 5V tolerant.  
1461A—07/28/09  
3
1234567...17

下载PDF

与9LPRS535CGLF相关器件

型号 品牌 描述 获取价格 数据表
9LPRS535CGLFT IDT 48-pin CK505 for Intel Systems

获取价格
9LPRS545BFLF IDT Microprocessor Circuit, PDSO48, 0.300 INCH, MO-118, SSOP-48

获取价格
9LPRS545BGLF IDT Microprocessor Circuit, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48

获取价格
9LPRS545BGLFT IDT Microprocessor Circuit, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48

获取价格
9LPRS545CFLF IDT Microprocessor Circuit, PDSO48, 0.300 INCH, MO-118, SSOP-48

获取价格
9LPRS545CFLFT IDT Microprocessor Circuit, PDSO48, 0.300 INCH, MO-118, SSOP-48

获取价格

与9LPRS535CGLF相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证