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9LPRS525AGLF PDF预览

9LPRS525AGLF

更新时间： 2024-02-02 14:40:27
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
21页 235K
描述
TSSOP-56, Tube

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9LPRS525AGLF 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.3
Samacsys Confidence：3Samacsys Status：Released
2D Presentation：https://componentsearchengine.com/2D/0T/1284768.2.1.pngSchematic Symbol：https://componentsearchengine.com/symbol.php?partID=1284768
PCB Footprint：https://componentsearchengine.com/footprint.php?partID=12847683D View：https://componentsearchengine.com/viewer/3D.php?partID=1284768
Samacsys PartID：1284768Samacsys Image：https://componentsearchengine.com/Images/9/9LPRS525AGLF.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/2/9LPRS525AGLF.jpgSamacsys Pin Count：56
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Small Outline Packages
Samacsys Footprint Name：PAG56_Samacsys Released Date：2020-01-17 12:09:31
Is Samacsys：NJESD-30 代码：R-PDSO-G56
JESD-609代码：e3长度：14 mm
湿度敏感等级：1端子数量：56
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Clock Generators
最大压摆率：200 mA最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：6.1 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

9LPRS525AGLF 数据手册

 浏览型号9LPRS525AGLF的Datasheet PDF文件第1页浏览型号9LPRS525AGLF的Datasheet PDF文件第2页浏览型号9LPRS525AGLF的Datasheet PDF文件第4页浏览型号9LPRS525AGLF的Datasheet PDF文件第5页浏览型号9LPRS525AGLF的Datasheet PDF文件第6页浏览型号9LPRS525AGLF的Datasheet PDF文件第7页 
ICS9LPRS525  
PC MAIN CLOCK  
Pin Description (continued)  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
Complementary clock of low power differential SRC clock pair with integrated 33 ohm Rs/ Clock Request control D for either SRC1 or SRC4 pair.  
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before  
configuring this pin as a Clock Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC output is  
disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRD#_EN bit located in byte 5 of SMBUs  
address space.  
25  
SRCC3_LRS/CR#_D  
I/O  
Byte 5, bit 1  
0 = SRC3 enabled (default)  
1= CRD# enabled. Byte 5, bit 0 controls whether CRD# controls SRC1 or SRC4 pair  
Byte 5, bit 0  
0 = CRD# controls SRC1 pair (default),  
1= CRD# controls SRC4 pair  
26  
27  
28  
VDDSRCIO  
SRCT4_LRS  
SRCC4_LRS  
PWR  
OUT  
OUT  
Power supply for SRC outputs. 1.05V to 3.3V.  
True clock of low power differential SRC clock pair with integrated 33 ohm Rs.  
Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.  
Stops all CPUCLK, except those set to be free running clocks /  
29  
30  
CPU_STOP#/SRCC5_LRS  
PCI_STOP#/SRCT5_LRS  
I/O  
I/O  
Complement clock of low power differential SRC pair with 33 ohm integrated Rs.  
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. / True clock of low power differential SRC pair  
with integrated 33 ohm Rs.  
31  
32  
33  
34  
VDDSRC  
PWR  
OUT  
OUT  
PWR  
Supply for SRC PLL, 3.3V nominal  
SRCC6_LRS  
SRCT6_LRS  
GNDSRC  
Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.  
True clock of low power differential SRC clock pair with integrated 33 ohm Rs.  
Ground pin for the SRC outputs  
Complement clock of differential push-pull SRC clock pair with 33 ohm integrated Rs. / Clock Request control E for SRC6 pair. The power-up default  
is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the  
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be  
35  
SRCC7_LRS/CR#_E  
I/O  
set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space  
Byte 6, bit 7  
0 = SRC7# enabled (default)  
1= CRE# enabled.  
True clock of differential push-pull SRC clock pair/ Clock Request control 8 for SRC8 pair  
36  
37  
SRCT7_LRS/CR#_F  
VDDSRCIO  
I/O  
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock  
Request Pin, the SR  
Power supply for SRC outputs. 1.05V to 3.3V.  
PWR  
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is  
determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:  
38  
CPUC2_ITP_LRS/SRCC8_LRS  
OUT  
OUT  
Pin 7 latched input Value  
0 = SRC8#  
1 = ITP#  
True clock of low power differential CPU2/True clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is determined by the  
latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:  
Pin 7 latched input Value  
0 = SRC8  
39  
CPUT2_ITP_LRS/SRCT8_LRS  
1 = ITP  
40  
41  
NC  
N/A  
PWR  
No Connect  
Power supply for CPU outputs, 1.05V to 3.3V.  
VDDCPUIO  
42  
CPUC1_F_LRS  
OUT  
Complementary clock of low power differential push-pull CPU output with integrated 33 ohm Rs. This CPU clock is free running during iAMT.  
43  
44  
45  
46  
47  
48  
CPUT1_F_LRS  
GNDCPU  
OUT  
PWR  
OUT  
OUT  
PWR  
IN  
True clock of differential push-pull CPU clock pair with integrated 33 ohm Rs. This clock is free running during iAMT.  
Ground pin for the CPU outputs  
CPUC0_LRS  
CPUT0_LRS  
VDDCPU  
Complement clock of low power differential CPU clock pair with integrated 33 ohm Rs.  
True clock of low power differential CPU clock pair with integrated 33 ohm Rs.  
Supply for CPU PLL, 3.3V nominal  
CK_PWRGD/PD#  
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode  
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time  
input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.  
Ground pin for the REF outputs.  
49  
FSLB/TEST_MODE  
IN  
50  
51  
52  
53  
GNDREF  
X2  
PWR  
OUT  
IN  
Crystal output, Nominally 14.318MHz  
Crystal input, Nominally 14.318MHz.  
X1  
VDDREF  
PWR  
Ref, XTAL power supply, nominal 3.3V  
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.  
/TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table  
Data pin for SMBus circuitry, 5V tolerant.  
54  
REF0/FSLC/TEST_SEL  
I/O  
55  
56  
SDATA  
SCLK  
I/O  
IN  
Clock pin of SMBus circuitry, 5V tolerant.  
IDTTM/ICSTM PC MAIN CLOCK  
1484A—04/28/09  
3
1234567...21

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