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9LPRS502YGLFT

更新时间： 2024-01-24 21:01:46
品牌 Logo 应用领域
艾迪悌 - IDT 稳压器微控制器和处理器外围集成电路uCs集成电路uPs集成电路光电二极管
页数 文件大小 规格书
29页 281K
描述
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

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9LPRS502YGLFT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：DFN
包装说明：ROHS COMPLIANT, MLF-56针数：56
Reach Compliance Code：compliantHTS代码：8542.31.00.01
风险等级：5.62Is Samacsys：N
JESD-30 代码：S-PQCC-N56JESD-609代码：e3
长度：8 mm端子数量：56
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1 mm最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：8 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

9LPRS502YGLFT 数据手册

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ICS9LPRS502  
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR  
Advance Information  
SSOP/TSSOP Pin Description  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair  
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of  
SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI  
output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is  
disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or  
pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space.  
1
2
3
PCI0/CR#_A  
I/O  
Byte 5, bit 7  
0 = PCI0 enabled (default)  
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair  
Byte 5, bit 6  
0 = CR#_A controls SRC0 pair (default),  
1= CR#_A controls SRC2 pair  
VDDPCI  
PWR  
Power supply pin for the PCI outputs, 3.3V nominal  
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair  
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of  
SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI  
output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is  
disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or  
pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space.  
Byte 5, bit 5  
PCI1/CR#_B  
I/O  
0 = PCI1 enabled (default)  
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair  
Byte 5, bit 4  
0 = CR#_B controls SRC1 pair (default)  
1= CR#_B controls SRC4 pair  
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-  
up as follows  
4
5
PCI2/TME  
PCI3  
I/O  
0 = Overclocking of CPU and SRC Allowed  
1 = Overclocking of CPU and SRC NOT allowed  
After being sampled on power-up, this pin becomes a 3.3V PCI Output  
3.3V PCI clock output.  
OUT  
3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the  
logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is  
enabled (pins 29 and 30). The latched value controls the pin function on pins 29 and 30 as follows  
0 = PCI_STOP#/CPU_STOP#  
6
PCI4/SRC5_EN  
I/O  
1 = SRC5/SRC5#  
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state  
of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an  
7
PCI_F5/ITP_EN  
I/O  
ITP or SRC pair.  
0 =SRC8/SRC8#  
1 = ITP/ITP#  
8
9
GNDPCI  
VDD48  
PWR  
PWR  
Ground for PCI clocks.  
Power supply for USB clock, nominal 3.3V.  
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to  
input electrical characteristics for Vil_FS and Vih_FS values.  
Ground pin for the 48MHz outputs.  
10  
USB_48MHz/FSLA  
I/O  
11  
12  
GND48  
PWR  
PWR  
VDD96_IO  
Power supply for DOT96 output. 1.05 to 3.3V +/-5%.  
True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin  
function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows:  
0= SRC0  
1=DOT96  
Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this  
pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows  
0= SRC0#  
1=DOT96#  
13  
14  
DOTT_96/SRCT0  
DOTC_96/SRCC0  
OUT  
OUT  
15  
16  
GND  
VDD  
PWR  
PWR  
Ground pin for the DOT96 clocks.  
Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.  
IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor  
1125E—02/26/09  
2
1234567...29

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