9LPRS436C
Low Power Clock for Intel Atom®-Based Systems
Electrical Characteristics - Absolute Maximum Ratings
MIN
TYP
MAX
4.6
4.6
PARAMETER
SYMBOL
VDDA
VDD
CONDITIONS
UNITS NOTES
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
V
V
V
V
1,2
1,2
1
Input Low Voltage
Input High Voltage
Input High Voltage
VIL
VIH
GND-0.5
Except for SMBus interface
SMBus clock and data pins
VDD+0.5V
5.5V
1
1
VIHSMB
V
Storage Temperature
Case Temperature
Input ESD protection
Ts
Tcase
ESD prot
-65
150
115
°C
°C
V
1
1
1
Human Body Model
2000
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Output DC Parameters
PARAMETER
SYMBOL
Tamb C
CONDITIONS
MIN
0
TYP
MAX
85
UNITS Notes
Standard Device
°C
°C
V
Ambient Operating Temp
TambI
Industrial Temperature Range Device
-40
85
Supply Voltage
Input High Voltage
VDDxxx
VIHSE
Supply Voltage
Single-ended 3.3V inputs
3.135
2
3.465
VDD + 0.3
V
7
7
Input Low Voltage
VILSE
VIH_FS4
VIL_ FS4
VIH_FS
Single-ended 3.3V inputs
Single-ended 3.3V FS(4:3) Inputs
Single-ended 3.3V FS(4:3) Inputs
3.3 V +/-5%
VSS - 0.3
0.8
VDD + 0.3
0.8
V
FS(4:3) Input High Voltage
2
V
V
V
V
SS - 0.3
FS(4:3) Input Low Voltage
Low Threshold Input-
0.7
VDD+0.3
High Voltage
Low Threshold Input-
Low Voltage
Input Leakage Current
VIL_FS
IIN
3.3 V +/-5%
VSS - 0.3
-5
0.35
5
V
VIN = VDD , VIN = GND
Inputs with pull up or pull down resistors
VIN = VDD , VIN = GND
Single-ended outputs, IOH = -1mA
Single-ended outputs, IOL = 1 mA
Full Active, CL = Full load; IDD 3.3V
Full Active, CL = Full load; IDD 3.3V
3.3V Main Rail
uA
uA
6
IINRES
Input Leakage Current
-200
2.4
200
Output High Voltage
Output Low Voltage
VOHSE
VOLSE
V
V
5
5
0.4
115
15
0
15
4
IDDVDD3.3
IDDVDDSUSP3 .3
IDDPDVDD3.3
IDDPDSUSP3.3w
IDDPDSUSP3.3
Fi
106
12
mA
mA
mA
mA
mA
MHz
nH
pF
pF
pF
V
Operating Supply Current
Powerdown Current
VDD_SUSP Rail. 25MHz Running (WOL)
VDD_SUSP Rail. 25MHz Off
VDD = 3.3 V
12
3
Input Frequency
Pin Inductance
27
7
8
Lpin
CIN
Logic Inputs
Output pin capacitance
X1 & X2 pins
1.5
5
6
Input Capacitance
COUT
CINX
6
VDD
SMBus Voltage
Low-level Output Voltage
Current sinking at
VOLSMB = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
2.7
4
5.5
0.4
VOLSMB
@ IPUL LUP
V
IPULLUP
TRI2C
SMB Data Pin
mA
ns
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
1000
300
TFI2C
ns
Clock/Data Fall Time
Maximum SMBus Operating Frequency
FSMBUS
fSSM OD
100
33
kHz
kHz
Spread Spectrum Modulation Frequency
Triangular Modulation
30
32.5
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1 Operation at these points is not recommended
2 Maximum VIH is not to exceed VDD
3 Human Body Model
4 Operation under these conditions is neither implied, nor guaranteed.
5Signal is required to be monotonic in this region.
6 Input leakage current does not include inputs with pull-up or pull-down resistors
7 3.3V referenced inputs are: PCI&PCIEX_STOP#, CPU_STOP#, ITP_EN, SCLK, SDATA, VTT_PWR_GD/PD#, SEL12_48# and PEREQ# inputs if selected.
8 For margining purposes only. Normal operation should have Fin = 25MHz +/-50ppm
IDT® Low Power Clock for Intel Atom®-Based Systems
1561C — 08/24/11
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