Datasheet > 9FGV1006Q5hhLTGI8

9FGV1006Q5hhLTGI8

更新时间： 2024-09-26 01:05:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	213K
描述
Low Phase-Noise, Low-Power Programmable PhiClock Generator

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Low Phase-Noise, Low-Power

Programmable PhiClock™ Generator

9FGV1006

Datasheet

Description

Features

▪ 1.8V to 3.3V V_DDs and V_DDREF

The 9FGV1006 is a member of IDT's PhiClock™ programmable

clock generator family. The 9FGV1006 provides two copies of a

single integer, fractional or spread spectrum output frequency and

one copy of the crystal reference input. Two select pins allow for

hardware selection of the desired configuration, or two I²C bits

allow easy software selection of the desired configuration. The

user may configure any one of the four OTP configurations as the

default when operating in I²C mode. Four unique I²C addresses

are available, allowing easy I²C access to multiple components.

▪ Individual 1.8V to 3.3V V_DDOfor each output pair

▪ Supports HCSL, LVDS and LVCMOS I/O standards

▪ Supports LVPECL and CML logic with easy AC coupling – see

application note AN-891 for alternate terminations

▪ HCSL utilizes IDT's LP-HCSL technology for improved

performance, lower power and higher integration:

ꢀ Programmable output impedance of 85 or 100Ω

▪ On-board OTP supports up to 4 complete configurations

▪ Configuration selected via strapping pins or I²C

Typical Applications

▪ HPC

▪ < 100mW at 1.8V, < 200mW at 3.3V with outputs running at

▪ Storage

100MHz

▪ 4 programmable I²C addresses: D0/D1, D2/D3, D4/D5, D6/D7

▪ 10G/25G Ethernet

▪ Fiber Optic Modules

▪ SSDs

read/write

▪ Supported by IDT Timing Commander™ software

▪ 3 × 3 mm 16-LGA with integrated crystal option (9FGV1006Q)

▪ NVLink

Key Specifications

Output Features

▪ 298fs rms typical phase jitter outputs at 156.25MHz (12kHz–

▪ 1 integer, fractional or spread spectrum output frequency per

20MHz)

configuration

▪ PCIe Gen1– 4 compliant

▪ 2 programmable output pairs plus 1 LVCMOS REF output

▪ 10MHz–325MHz output frequency (LVDS or LP-HCSL), integer

PCIe Clocking Architectures

configuration

▪ Common Clocked (CC)

▪ 10MHz–200MHz output frequency (LVCMOS), integer

configuration

▪ Independent Reference without spread spectrum (SRnS)

▪ Independent Reference with spread spectrum (SRIS)

▪ 10MHz–156.25MHz output frequency (LVDS or LP-HCSL),

fractional or spread spectrum configuration

Block Diagram

OTP_VPP

VDDDp

VDDAp VDDAO0p

XIN/CLKIN

OSC

REF0

VDDREFp

Fractional

PLL

(SSC)

OUT1#

OUT1

INT

DIV

VDDO1

OUT0#

OUT0

VDDO0

vSEL_I2C#

^SEL0/SCL

^SEL1/SDA

SMBus

Engine

Factory

Configuration

Control Logic

Internal terminations are available when LP-HCSL output format is selected.

EPAD/GND

July 5, 2018

12 3 4 5 6 7...15

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