Datasheet > 9FGV1008

9FGV1008

更新时间： 2024-10-15 14:57:27

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
29页	1096K
描述
Programmable PhiClock? Generator

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数据手册

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9FGV1008 数据手册

Low Phase-Noise, Low-Power

Programmable PhiClock™

Generator

9FGV1004C/9FGV1008C

Datasheet

Description

Features

▪ 1.8V, 2.5V or 3.3V power supplies

The 9FGV1004C/9FGV1008C are members of Renesas’

PhiClock™ programmable clock generator family. The 9FGV1004

provides 1 copy each of 2 integer-related frequencies, 2 copies of

a fractional or spread-spectrum frequency. The 9FGV1008

provided 1 integer frequency and 1 copy of a fractional or

spread-spectrum frequency. Four user-defined configurations may

be selected via two hardware select pins or two I²C bits, allowing

easy software selection of the desired configuration. Any one of

the four OTP configurations may be specified as the default when

operating in I²C mode. Four unique I²C addresses are available,

allowing easy I²C access to multiple components.

▪ Individual V_DDOfor each programmable output pair

▪ Supports HCSL, LVDS and LVCMOS I/O standards

▪ Low-Power HCSL technology for improved performance, lower

power and higher integration:

• Programmable output impedance of 85Ω or 100Ω

▪ Supports LVPECL and CML logic with easy AC coupling – see

AN-891 for alternate terminations

▪ On-board OTP supports up to 4 complete configurations

selectable via strapping pins or I²C

▪ Internal crystal load capacitors

Typical Applications

▪ Programmable spread-spectrum modulation frequency and

amount

▪ High-performance Computing (HPC)

▪ eSSDs

▪ < 150mW at 1.8V with LP-HCSL outputs at 100MHz

(9FGV1004)

▪ 10G/25G/100G Ethernet

▪ Fiber Optic Modules

▪ < 135mW at 1.8V with LP-HCSL outputs at 100MHz

(9FGV1008)

▪ Data Center Accelerators

▪ 4 programmable I²C addresses: D0, D2, D4, D6

Output Features

▪ 9FGV1004: 4 programmable output pairs plus 2 LVCMOS REF

outputs

▪ Easily configured with Renesas Timing Commander™ software

or Web Configurator

▪ Space saving 4 × 4 mm 24-VFQFPN, 24-LGA (9FGV1004) and

3 × 3 mm 16-LGA (9FGV1008) packages

▪ 9FGV1008 2 programmable output pairs plus 1 LVCMOS REF

output

▪ Integrated crystal option (9FGV1004CQ, 9FGV1008CQ)

▪ 2 integer and 1 fractional/spread spectrum output frequency

per configuration

Key Specifications

▪ 12kHz–20MHz typical phase jitter at156.25M Hz (SSC off or

on) 224fs RMS (9FGV1008 OUT1)

▪ 1MHz–325MHz LVDS or LP-HCSL outputs

▪ 1MHz–200MHz LVCMOS outputs

▪ 1MHz–156.25MHz spread spectrum or fractional output

▪ 12kHz–20MHz typical phase jitter at156.25MHz (SSC off or on)

267fs RMS (9FGV1004 OUT3)

PCIe Clocking Architectures

▪ Common Clocked (CC)

▪ PCIe Gen1–4 compliant (spread spectrum off)

▪ PCIe Gen1–3 compliant (spread spectrum on)

▪ Independent Reference without spread spectrum (SRnS)

▪ See AN1001 for generating PCIe Gen5 clocks from the

9FGV1004C/9FGV1008C

▪ See AN1001 for Independent Reference with spread-spectrum

(SRIS) applications

March 29, 2023

12 3 4 5 6 7...29

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