Datasheet > 9FGU0231AKILF

9FGU0231AKILF

更新时间： 2022-02-26 10:49:51

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
15页	197K
描述
2 O/P 1.5V PCIe Gen1-2-3 Clock Generator

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数据手册

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9FGU0231AKILF 数据手册

9FGU0231 DATASHEET

SMBus Table: Output Enable Register

Byte 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Control Function

Reserved

Type

Default

Reserved

DIF OE1

DIF OE0

Output Enable

Reserved

Low/Low

Enabled

SMBus Table: SS Readback and Vhigh Control Register

Byte 1

Bit 7

Bit 6

Name

SSENRB1

Control Function

SS Enable Readback Bit1

SS Enable Readback Bit0

Type

Default

Latch

00' for SS_EN_tri = 0, '01' for SS_EN_tri

= 'M', '11 for SS_EN_tri = '1'

Values in B1[4:3]

SS control locked

SSEN_SWCNTRL

Enable SW control of SS

Bit 5

control SS amount.

RW¹

SSENSW1

SSENSW0

SS Enable Software Ctl Bit1

SS Enable Software Ctl Bit0

Reserved

00' = SS Off, '01' = -0.25% SS,

'10' = Reserved, '11'= -0.5% SS

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

AMPLITUDE 1

AMPLITUDE 0

00 = 0.55V

10= 0.7V

01 = 0.65V

11 = 0.8V

Controls Output Amplitude

1. B1[5] must be set to a 1 for these bits to have any effect on the part.

SMBus Table: DIF Slew Rate Control Register

Byte 2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Control Function

Reserved

Type

Default

Reserved

SLEWRATESEL DIF1

SLEWRATESEL DIF0

Adjust Slew Rate of DIF1

Adjust Slew Rate of DIF0

Reserved

Slow Setting

Fast Setting

SMBus Table: REF Control Register

Byte 3

Bit 7

Bit 6

Name

Control Function

Type

Default

00 = Slowest

10 = Fast

01 = Slow

11 = Faster

REF

Slew Rate Control

REF does not run in REF runs in Power

REF Power Down Function

REF OE

Wake-on-Lan Enable for REF

REF Output Enable

Bit 5

Power Down

Low

Down

Enabled

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Byte 4 is reserved and reads back 'hFF'.

2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR

OCTOBER 18, 2016

1...7 8 91011 12 13...15

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