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9FGP205AKLF

更新时间： 2024-02-03 10:08:36
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
18页 257K
描述
Frequency Timing Generator for Peripherals

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9FGP205AKLF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：VFQFPN
包装说明：HVQCCN, LCC40,.24SQ,20针数：40
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：4.51
Samacsys Description：VFQFP-N 6.0 X 6.0 X 0.9 MM - NO LEADJESD-30 代码：S-PQCC-N40
JESD-609代码：e3长度：6 mm
湿度敏感等级：3端子数量：40
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：400 MHz封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC40,.24SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：25 MHz认证状态：Not Qualified
座面最大高度：1 mm子类别：Clock Generators
最大压摆率：225 mA最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：6 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC

9FGP205AKLF 数据手册

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9FGP205  
Advance Information  
Frequency Timing Generator for Peripherals  
Pin Description  
PIN  
PIN #  
PIN NAME  
DESCRIPTION  
TYPE  
PWR  
PWR  
1
2
GND  
VDD96  
Ground pin.  
Power pin for the DOT96 clocks, nominal 3.3V  
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock. These are  
current mode outputs. External resistors are required for voltage bias.  
Complementary clock of differential pair for 96.00MHz spread spectrum capable DOT clock.  
These are current mode outputs. External resistors are required for voltage bias.  
Active high input for enabling 96Hz outputs.  
1 = enable output(s), 0 = tri-state output(s)  
Active high input for enabling CPU DIFF pairs.  
1 = enable output(s), 0 = tri-state output(s)  
True clock of differential pair CPU outputs. These are current mode outputs. External resistors  
are required for voltage bias.  
3
4
5
6
7
DOT96SST  
DOT96SSC  
OE_96  
OUT  
OUT  
IN  
OE_CPU  
IN  
CPUCLKT0  
OUT  
OUT  
Complementary clock of differential pair CPU outputs. These are current mode outputs.  
External resistors are required for voltage bias.  
Supply for CPU clocks, 3.3V nominal  
8
9
CPUCLKC0  
VDDCPU  
PWR  
PWR  
10 GNDCPU  
Ground pin for the CPU outputs  
This pin establishes the reference current for the differential current-mode output pairs. This pin  
requires a fixed precision resistor tied to ground in order to establish the appropriate current.  
475 ohms is the standard value.  
11 IREF  
OUT  
12 VDD32K  
13 32.768KHz  
14 GND32K  
15 VDDREF  
16 25MHz_0  
17 25MHZ_1  
18 GNDREF  
19 X1_25  
PWR  
OUT  
PWR  
PWR  
OUT  
OUT  
PWR  
IN  
Power pin for the 32.768KHz outputs, nominal 3.3V  
32.768KHz clock output  
Ground pin for the 32.768KHz outputs  
Ref, XTAL power supply, nominal 3.3V  
25MHz clock output, 3.3V  
25MHz clock output, 3.3V  
Ground pin for the REF outputs.  
Crystal input, Nominally 25.00MHz.  
20 X2_25  
21 GND33  
OUT  
PWR  
Crystal output, Nominally 25.00MHz.  
Ground pin for the 33.33MHz outputs  
22 33.33MHZ/**SMBADR  
I/O  
33.33MHz clock output / SMBus address select bit.  
23 VDD33  
24 RMII5  
25 RMII4  
26 VDDRMII  
27 GNDRMII  
28 RMII3  
PWR  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
IN  
Power pin for the 33.33MHz outputs, nominal 3.3V  
3.3V 50MHz RMII clock output  
3.3V 50MHz RMII clock output  
3.3V power pin for the RMII clocks.  
Ground pin for the RMII outputs  
3.3V 50MHz RMII clock output  
3.3V 50MHz RMII clock output  
Ground pin for the RMII outputs  
3.3V power pin for the RMII clocks.  
3.3V 50MHz RMII clock output  
3.3V 50MHz RMII clock output  
3.3V power pin for the RGMII clocks and PLL  
Ground pin for the RGMII outputs  
3.3V 125MHz RGMII clock output  
3.3V 125MHz RGMII clock output  
Clock pin of SMBUS circuitry, 5V tolerant  
Data pin of SMBUS circuitry, 5V tolerant  
29 RMII2  
30 GNDRMII  
31 VDDRMII  
32 RMII1  
33 RMII0  
34 VDDRGMII  
35 GNDRGMII  
36 RGMII1  
37 RGMII0  
38 SMBCLK  
39 SMBDAT  
I/O  
Notifies clock to sample latched inputs on first low to high transition. After first power up, a low  
stops all outputs except those designated to run in power down mode (WOL_STOP# mode)  
40 CKPWRGD_WOL_STOP#  
IN  
IDT® Frequency Timing Generator for Peripherals  
1664—05/14/10  
2
1234567...18

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