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9FGP202AKLF PDF预览

9FGP202AKLF

更新时间： 2024-02-18 19:45:28
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路PC
页数 文件大小 规格书
19页 231K
描述
FREQUENCY TIMING GENERATOR FOR PERIPHERALS

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9FGP202AKLF 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：VFQFPN
包装说明：HVQCCN, LCC40,.24SQ,20针数：40
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.01
Samacsys Confidence：3Samacsys Status：Released
2D Presentation：https://componentsearchengine.com/2D/0T/824243.2.1.pngSchematic Symbol：https://componentsearchengine.com/symbol.php?partID=824243
PCB Footprint：https://componentsearchengine.com/footprint.php?partID=8242433D View：https://componentsearchengine.com/viewer/3D.php?partID=824243
Samacsys PartID：824243Samacsys Image：https://componentsearchengine.com/Images/9/9FGP202AKLFT.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/2/9FGP202AKLFT.jpgSamacsys Pin Count：41
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Quad Flat No-Lead
Samacsys Footprint Name：NLG40P1Samacsys Released Date：2020-02-02 05:03:22
Is Samacsys：NJESD-30 代码：S-PQCC-N40
JESD-609代码：e3长度：6 mm
湿度敏感等级：3端子数量：40
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：33.33 MHz封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC40,.24SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：25 MHz认证状态：Not Qualified
座面最大高度：1 mm子类别：Clock Generators
最大压摆率：200 mA最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

9FGP202AKLF 数据手册

 浏览型号9FGP202AKLF的Datasheet PDF文件第1页浏览型号9FGP202AKLF的Datasheet PDF文件第2页浏览型号9FGP202AKLF的Datasheet PDF文件第4页浏览型号9FGP202AKLF的Datasheet PDF文件第5页浏览型号9FGP202AKLF的Datasheet PDF文件第6页浏览型号9FGP202AKLF的Datasheet PDF文件第7页 
9FGP202A  
FREQUENCY TIMING GENERATOR FOR PERIPHERALS  
Pin Descriptions  
PIN #  
PIN NAME  
PIN TYPE  
DESCRIPTION  
1
2
3
4
GND  
VDD96  
DOT96SST  
DOT96SSC  
PWR  
PWR  
OUT  
OUT  
Ground pin.  
Power pin for the DOT96 clocks, nominal 3.3V  
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock.  
Complement clock of differential pair for 96.00MHz spread spectrum capable DOT clock.  
Active high input for enabling 96Hz outputs.  
1 = enable output(s), 0 = tri-state output(s)  
Active high input for enabling CPU DIFF pairs.  
1 = enable output(s), 0 = tri-state output(s)  
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are  
required for voltage bias.  
Complementary clock of differential pair CPU outputs. These are current mode outputs. External  
resistors are required for voltage bias.  
Supply for CPU clocks, 3.3V nominal  
Ground pin for the CPU outputs  
5
6
7
OE_96  
IN  
OE_CPU  
CPUCLKT0  
IN  
OUT  
OUT  
8
9
CPUCLKC0  
VDDCPU  
PWR  
PWR  
10 GNDCPU  
This pin establishes the reference current for the differential current-mode output pairs. This pin  
11 IREF  
OUT  
requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475  
ohms is the standard value.  
12 VDD32K  
13 32.768KHz  
14 GND32K  
15 VDDREF  
16 25MHz_0  
17 25MHZ_1  
18 GNDREF  
19 X1_25  
PWR  
OUT  
PWR  
PWR  
OUT  
OUT  
PWR  
IN  
Power pin for the 32.768KHz outputs, nominal 3.3V  
32.768KHz clock output  
Ground pin for the 32.768KHz outputs  
Ref, XTAL power supply, nominal 3.3V  
25MHz clock output, 3.3V  
25MHz clock output, 3.3V  
Ground pin for the REF outputs.  
Crystal input, Nominally 25.00MHz.  
Crystal output, Nominally 25.00MHz.  
Ground pin for the 33.33MHz outputs  
20 X2_25  
21 GND33  
OUT  
PWR  
22 33.33MHZ/**SMBADR  
I/O  
33.33MHz clock output / SMBus address select bit.  
23 VDD33  
24 RMII7  
25 RMII6  
26 VDDRMII  
27 GNDRMII  
28 RMII5  
PWR  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
Power pin for the 33.33MHz outputs, nominal 3.3V  
3.3V RMII clock output  
3.3V RMII clock output  
3.3V power pin for the RMII clocks.  
Ground pin for the 3V50 outputs  
3.3V RMII clock output  
29 RMII4  
3.3V RMII clock output  
Active high input for enabling RMII(7:4) outputs.  
1 = enable output(s), 0 = low  
Active high input for enabling RMII(3:0) outputs.  
1 = enable output(s), 0 = low  
30 OE_RMIIB  
31 OE_RMIIA  
IN  
IN  
32 RMII3  
33 RMII2  
34 VDDRMII  
35 GNDRMII  
36 RMII1  
37 RMII0  
38 SMBCLK  
39 SMBDAT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
IN  
3.3V RMII clock output  
3.3V RMII clock output  
3.3V power pin for the RMII clocks.  
Ground pin for the 3V50 outputs  
3.3V RMII clock output  
3.3V RMII clock output  
Clock pin of SMBUS circuitry, 5V tolerant  
Data pin of SMBUS circuitry, 5V tolerant  
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and  
are ready to be sampled. This is an active high input. / Asynchronous active low input pin used to  
power down the device into a low power state.  
I/O  
40 VttPwr_GD/PD#  
IN  
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS  
3
9FGP202A  
REV D 070511  
1234567...19

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