Datasheet > 9FGL0251BKILFT

9FGL0251BKILFT

更新时间： 2022-02-26 10:49:50

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	370K
描述
2-output 3.3V PCIe Clock Generator

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数据手册

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9FGL0251BKILFT 数据手册

9FGL02 DATASHEET

Pin Configuration

24 23 22 21 20 19

XIN/CLKIN_25 1

X2 2

DIF1#

DIF1

9FGL02xx

ePAD is

GND

VDDXTAL3.3 3

vSADR/REF3.3 4

VDDA3.3

GNDA

DIF0#

GNDREF

GNDDIG

13 DIF0

9 10 11 12

24-pin VFQFPN, 4x4 mm, 0.5mm pitch

^ prefix indicates internal 120KOhm pull up resistor

v prefix indicates internal 120KOhm pull down resistor

SMBus Address Selection Table

Read/Write Bit

SADR

Address

1101000

1101010

State of SADR on first application

of CKPWRGD_PD#

Power Management Table

DIF

True O/P Comp. O/P

SMBus

OE bit

REF

CKPWRGD_PD#

Low¹

Running

Disabled¹

Low¹

Running

Disabled¹

Disabled¹Disabled⁴

Hi-Z²

Running

1. The output state is set by B11[1:0] (Low/Low default)

2. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After

this, when CKPWRG_PD# is low, REF is disabled unless

Byte3[5]=1, in which case REF is running..

3. Input polarities defined at default values for 9FGLxx41/xx51.

4. See SMBus description for Byte 3, bit 4

Power Connections

Pin Number

Description

VDD

11,20

GND

5,24

10,21,25

XTAL, REF

Digital Power

DIF outputs

PLL Analog

2-OUTPUT 3.3V PCIE CLOCK GENERATOR

OCTOBER 18, 2016

123 4 5 6 7...19

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