Datasheet > 9FGL02

9FGL02

更新时间： 2022-02-26 10:49:50

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	370K
描述
2-output 3.3V PCIe Clock Generator

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9FGL02 数据手册

9FGL02 DATASHEET

Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating

Conditions

TA = T_AMB;Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

Supply Voltage

SYMBOL

VDDxxx

CONDITIONS

MIN

TYP

3.3

MAX

UNITS NOTES

Supply voltage for core, analog and single-

ended LVCMOS outputs.

3.135

3.465

Commmercial range

Industrial range

-40

°C

Ambient Operating

Temperature

T_AMB

Input High Voltage

Input Low Voltage

Input High Voltage

V_IH

V_IL

0.75 V_DDx

-0.3

V_DDx+ 0.3

0.25 V_DDx

V_DD+ 0.3

Single-ended inputs, except SMBus

V_IHtri

0.75 V_DDx

Single-ended tri-level inputs ('_tri' suffix)

Input Mid Voltage

Input Low Voltage

V_IMtri

0.4 V_DDx0.5 V_DDx0.6 V_DDx

V_ILtri

I_IN

-0.3

-5

0.25 V_DDx

Single-ended inputs, V_IN= GND, V_IN= VDD

Single-ended inputs

Input Current

V_IN= 0 V; Inputs with internal pull-up resistors

I_INP

-50

_IN= VDD; Inputs with internal pull-down

resistors

Input Frequency

Pin Inductance

F_in

L_pin

XTAL, or X1 input

MHz

C_IN

Logic Inputs, except DIF_IN

Output pin capacitance

1.5

Capacitance

C_OUT

From V_DDPower-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

Clk Stabilization

T_STAB

0.34

31.6

1.8

1,2

Allowable Frequency

(Triangular Modulation)

DIF start after OE# assertion

DIF stop after OE# deassertion

DIF output enable after

SS Modulation Frequency

OE# Latency

f_MOD

t_LATOE#

t_DRVPD

kHz

clocks

1,3

Tdrive_PD#

300

PD# de-assertion

Tfall

t_F

Fall time of single-ended control inputs

1,2

Trise

t_R

Rise time of single-ended control inputs

¹Guaranteed by design and characterization, not 100% tested in production.

²Control input must be monotonic from 20% to 80% of input swing.

³Time from deassertion until outputs are >200 mV

⁴The 9FGLxxP1 devices can be programmed for various input frequencies from 8 to 40MHz. The 9FGLxx41/51 devices use 25MHz.

2-OUTPUT 3.3V PCIE CLOCK GENERATOR

OCTOBER 18, 2016

1...3 4 567 8 9...19

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