5秒后页面跳转
9FGL02 PDF预览

9FGL02

更新时间: 2022-02-26 10:49:50
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
19页 370K
描述
2-output 3.3V PCIe Clock Generator

9FGL02 数据手册

 浏览型号9FGL02的Datasheet PDF文件第2页浏览型号9FGL02的Datasheet PDF文件第3页浏览型号9FGL02的Datasheet PDF文件第4页浏览型号9FGL02的Datasheet PDF文件第6页浏览型号9FGL02的Datasheet PDF文件第7页浏览型号9FGL02的Datasheet PDF文件第8页 
9FGL02 DATASHEET  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9FGL02. These ratings, which are standard values  
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions  
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating  
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended  
operating temperature range.  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX UNITS NOTES  
Supply Voltage  
Input Voltage  
VDDx  
VIN  
-0.5  
-0.5  
4.6  
VDD+0.5  
V
V
1,2  
1,3  
Input High Voltage, SMBus  
Storage Temperature  
Junction Temperature  
Input ESD protection  
VIHSMB  
Ts  
Tj  
SMBus clock and data pins  
Human Body Model  
3.9  
150  
125  
V
1
1
1
1
-65  
°C  
°C  
V
ESD prot  
2500  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
3 Not to exceed 4.6V.  
Electrical Characteristics–SMBus Parameters  
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX UNITS NOTES  
SMBus Input Low Voltage  
SMBus Input High Voltage  
VILSMB  
VIHSMB  
VDDSMB = 3.3V  
VDDSMB = 3.3V  
@ IPULLUP  
0.8  
3.6  
0.4  
V
V
2.1  
SMBus Output Low Voltage VOLSMB  
V
SMBus Sink Current  
Nominal Bus Voltage  
SCLK/SDATA Rise Time  
IPULLUP  
VDDSMB  
tRSMB  
@ VOL  
4
mA  
V
2.7  
3.6  
1000  
300  
(Max VIL - 0.15) to (Min VIH + 0.15)  
(Min VIH + 0.15) to (Max VIL - 0.15)  
ns  
ns  
1
1
SCLK/SDATA Fall Time  
SMBus Operating  
Frequency  
tFSMB  
fSMB  
SMBus operating frequency  
500  
kHz  
2
1 Guaranteed by design and characterization, not 100% tested in production.  
2. The device must be powered up for the SMBus to function.  
OCTOBER 18, 2016  
5
2-OUTPUT 3.3V PCIE CLOCK GENERATOR  

与9FGL02相关器件

型号 品牌 描述 获取价格 数据表
9FGL02_16 IDT 2-output 3.3V PCIe Clock Generator

获取价格

9FGL0241BKILF IDT 2-output 3.3V PCIe Clock Generator

获取价格

9FGL0241BKILFT IDT 2-output 3.3V PCIe Clock Generator

获取价格

9FGL0251BKILF IDT 2-output 3.3V PCIe Clock Generator

获取价格

9FGL0251BKILFT IDT 2-output 3.3V PCIe Clock Generator

获取价格

9FGL04 IDT 4-output 3.3V PCIe Clock Generator

获取价格