Datasheet > 9DBV0831_16

9DBV0831_16

更新时间： 2022-02-26 10:42:11

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	326K
描述
8-output 1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer

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9DBV0831_16 数据手册

8-output 1.8V PCIe Gen1/2/3

Zero-Delay/Fan-out Buffer (ZDB/FOB)

9DBV0831

DATASHEET

Description

Features/Benefits

The 9DBV0831 is a member of IDT's SOC-Friendly 1.8V

Very-Low-Power (VLP) PCIe family. It can also be used for

50M or 125M Ethernet Applications via software frequency

selection. The device has 8 output enables for clock

management, and 3 selectable SMBus addresses.

• LP-HCSL outputs save 16 resistors; minimal board space

and BOM cost

• 62mW typical power consumption in PLL mode; minimal

power consumption

• Spread Spectrum (SS) compatible; allows use of SS for

EMI reduction

Recommended Application

1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)

• OE# pins; support DIF power management

• HCSL compatible differential input; can be driven by

common clock sources

• Programmable Slew rate for each output; allows tuning for

Output Features

• 8 – 1-200Hz Low-Power (LP) HCSL DIF pairs

w/ZO=100ohms

various line lengths

• Programmable output amplitude; allows tuning for various

application environments

• Pin/software selectable PLL bandwidth and PLL Bypass;

minimize phase jitter for each application

Key Specifications

• Outputs blocked until PLL is locked; clean system start-up

• Software selectable 50MHz or 125MHz PLL operation;

useful for Ethernet applications

• DIF cycle-to-cycle jitter <50ps

• DIF output-to-output skew <50ps

• DIF additive phase jitter is <100fs rms for PCIe Gen3

• DIF additive phase jitter <300fs rms for 12k-20MHz

• Configuration can be accomplished with strapping pins;

SMBus interface not required for device control

• 3.3V tolerant SMBus interface works with legacy controllers

• Space saving 48-pin 6x6mm VFQFPN; minimal board

space

• Selectable SMBus addresses; multiple devices can easily

share an SMBus segment

Block Diagram

vOE(7:0)#

DIF7

DIF6

CLK_IN

CLK_IN#

SS-

DIF5

Compatible

PLL

DIF4

vSADR

DIF3

DIF2

DIF1

^vHIBW_BYPM_LOBW#

CONTROL

LOGIC

^CKPWRGD_PD#

SDATA_3.3

SCLK_3.3

DIF0

9DBV0831 REVISION H 04/28/16

12 3 4 5 6 7...19

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