Datasheet > 9DBL411

9DBL411

更新时间： 2023-12-20 18:45:39

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
14页	731K
描述
4-output 3.3 V PCIe Gen1-2-3 Fanout Buffer

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9DBL411 数据手册

9DBL411B Datasheet

Table 2. 20-TSSOP Pin Descriptions (Cont.)

Pin Type Description

Pin Number

Pin Name

Complement clock of low power differential clock pair (no 50ohm shunt resistor to

GND needed).

DIF2C_LPR

DIF2T_LPR

OE2#

Output

Input

True clock of low power differential clock pair (no 50ohm shunt resistor to GND

needed).

Output Enable for DIF2 output. Control is as follows:

0 = enabled, 1 = Low-Low

Complement clock of low power differential clock pair (no 50ohm shunt resistor to

GND needed).

DIF1C_LPR

DIF1T_LPR

OE1#

Output

Input

True clock of low power differential clock pair (no 50ohm shunt resistor to GND

needed).

Output Enable for DIF1 output. Control is as follows:

0 = enabled, 1 = Low-Low

GND

Ground pin.

VDD_IO

Power

Power supply for low power differential outputs, nominal 1.05V to 3.3V.

Complement clock of low power differential clock pair (no 50ohm shunt resistor to

GND needed).

DIF0C_LPR

DIF0T_LPR

Output

True clock of low power differential clock pair (no 50ohm shunt resistor to GND

needed).

1.3

Power Groups

Pin Number (VFQFPN)

Description

VDD

6, 15

GND

7, 14

VDD_IO for DIF(3:0)

3.3V Analog VDD & GND

Pin Number (TSSOP)

Description

VDD

9, 18

GND

10, 17

VDD_IO for DIF(3:0)

3.3V Analog VDD & GND

R31DS0147EU0108 Rev.1.08

Feb 6, 2023

Page 5

1 2 3 456 7 8...14

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