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9DBL0242 PDF预览

9DBL0242

更新时间: 2024-01-13 05:52:59
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
19页 300K
描述
2-output 3.3V PCIe Zero-Delay Buffer

9DBL0242 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN,针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:2.31Samacsys Description:Clock Buffer 2 O/P 3.3V PCIE ZERO DELAY BUF
系列:9DBL输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N24JESD-609代码:e3
长度:4 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:24
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260座面最大高度:1 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4 mmBase Number Matches:1

9DBL0242 数据手册

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9DBL0242 / 9DBL0252 DATASHEET  
Pin Configuration  
24 23 22 21 20 19  
FB_DNC 1  
FB_DNC# 2  
VDDR3.3 3  
CLK_IN 4  
DIF1#  
DIF1  
18  
17  
16  
15  
14  
9DBL0242/52/P2  
connect epad to  
GND  
VDDA3.3  
vOE0#  
DIF0#  
CLK_IN# 5  
GNDDIG 6  
13 DIF0  
7
8
9 10 11 12  
24-pin VFQFPN, 4x4 mm, 0.5mm pitch  
^ prefix indicates internal 120KOhm pull up resistor  
^v prefix indicates internal 120KOhm pull up AND  
pull down resistor (biased to VDD/2)  
v prefix indicates internal 120KOhm pull down  
resistor  
SMBus Address Selection Table  
+
Read/Write bit  
SADR  
Address  
1101011  
1101100  
1101101  
x
x
x
0
M
1
State of SADR on first application of  
CKPWRGD_PD#  
Note: If not using CKPWRGD (CKPWRGD tied to VDD3.3), all 3.3V VDD need to transition  
from 2.1V to 3.135V in <300usec.  
Power Management Table  
SMBus  
OE bit  
X
DIFx/DIFx#  
CKPWRGD_PD#  
CLK_IN  
OEx# Pin  
PLL  
True O/P  
Low1  
Comp. O/P  
Low1  
0
1
1
1
X
X
0
Off  
On3  
On3  
On3  
Running  
Running  
Running  
1
1
0
Running  
Disabled1  
Disabled1  
Running  
Disabled1  
Disabled1  
1
X
1. The output state is set by B11[1:0] (Low/Low default)  
2. Input polarities defined as default values for xx41/xx51 devices.  
3. If Bypass mode is selected, the PLL will be off, and outputs will be running.  
Power Connections  
PLL Operating Mode  
Pin Number  
Description  
Byte1 [7:6] Byte1 [4:3]  
VDD  
3
8
GND  
25  
6
HiBW_BypM_LoBW#  
MODE  
PLL Lo BW  
Bypass  
Readback  
Control  
00  
Input receiver analog  
Digital Power  
DIF outputs  
0
M
1
00  
01  
11  
01  
10,21  
16  
25  
PLL Hi BW  
11  
25  
PLL Analog  
2-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER  
2
FEBRUARY 8, 2017  

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