Datasheet > 9DB306LLF

9DB306LLF

更新时间： 2024-02-21 08:13:08

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	309K
描述
Clock Driver

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中文翻译

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技术参数
数据手册

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9DB306LLF 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.84	Base Number Matches：	1

9DB306LLF 数据手册

ICS9DB306

Integrated

Circuit

Systems, Inc.

PCI EXPRESS

JITTER

ATTENUATOR

SCHEMATIC EXAMPLE

Figure 5 shows an example of ICS9DB306 application

schematic.In this example, the device is operated atV_CC= 3.3V.

LVPECL output drivers, one of terminations approaches is shown

in this schematic. For additional termination approaches, please

The decoupling capacitor should be located as close as pos- refer to the LVPECLTermination Application Note.

sible to the power pin.The input is driven by a HCSL driver. For

Zo = 50

VCC

R11

Zo = 50

VCC

VCCA

LVPECL

ICS9DB306

VCC

C16

10uF

C11

0.1uF

VCC

VEE

PCIEXT4

PCIEXC4

PCIEXT3

PCIEXC3

VCC

PCIEXC5

PCIEXT5

FS1

BYPASS

VEE

VCCA

PLL_BW

CLK

nCLK

FS0

PCIEXT0

PCIEXC0

VCC

nOE1

nOE0

VCC

R12 33

Zo = 50

PCIEXC2

PCIEXT2

PCIEXC1

PCIEXT1

VEE

HCSL

R13 33

R10

Zo = 50

LVPECL

(U1-28)

(U1-9)

(U1-15)

(U1-6)

VCC

R14 R15

50 50

0.1uF

VCC=3.3V

R16

FIGURE 5. EXAMPLE OF ICS9DB306 SCHEMATIC

9DB306BL

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 22, 2004

1...7 8 91011 12 13...15

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