Datasheet > 9DB233

9DB233

更新时间： 2023-12-20 18:45:51

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
18页	370K
描述
2-output 3.3 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

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9DB233 数据手册

9DB233

TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3

Electrical Characteristics–PCIe Phase Jitter Parameters

TA = T_COMor T_IND;Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

t_jphPCIeG1

CONDITIONS

PCIe Gen 1

MIN

TYP

MAX

UNITS Notes

ps (p-p) 1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

PCIe Gen 3

(rms)

3.1

1,2

t_jphPCIeG2

Phase Jitter, PLL Mode

1,2

t_jphPCIeG3

t_jphPCIeG1

1,2,4

(rms)

(PLL BW of 2-4MHz, CDR = 10MHz)

PCIe Gen 1

ps (p-p) 1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

PCIe Gen 3

(rms)

0.2

0.3

1,2

Additive Phase Jitter,

Bypass Mode

t_jphPCIeG2

0.2

0.1

1,2

t_jphPCIeG3

1,2,4

(rms)

(PLL BW of 2-4MHz, CDR = 10MHz)

¹Applies to all outputs.

²See http://www.pcisig.com for complete specs

³Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

⁴Subject to final ratification by PCI SIG.

IDT® TWO OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3

9DB233

OCTOBER 20, 2016

1...4 5 678 9 10...18

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