9DB106
Six Output Differential Buffer for PCIe Gen 2
Revision History
Rev. Originator Issue Date Description
Page #
1. Changed Output to Output skew from 30ps to 45ps.
2. Changed PLL mode jitter from 40ps to 35ps.
3. Changed Bypass mode additive jitter from 25ps to 35ps.
4. Updated LF Ordering Information.
5,
B
C
D
RDW
RDW
RDW
9/12/2005
8/17/2006
3/12/2007
8-9
Corrected Typo of SMBus Read/Write Address.
7
6
Added SMBus Read/Write Table.
1. Added Phase Noise Parameters, Updated input to output delay values.
2. PLL BW moved to PLL parameters table.
E
F
RDW
RDW
8/6/2007 3. Added terminations tables.
6-8
9
12/14/2007 Updated SMBus serial Interface Information.
G
4/1/2010 Updated ordering info for Rev B
13
1. Updated DS to include I-temp specs and ordering information
2. Updated electrical tables to reflect common set of numbers for I-temp and C-temp
3. Converted all references of ICS to IDT
H
J
RDW
RDW
RDW
9/15/2010 4. Corrected placement of AC coupling caps in Figure 4
1/27/2011 Updated Termination Figure 4.
8
K
4/20/2011 1. Changed pull down indicator from '**" to " v " to correct pin description of CLKREQ# pins.
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