Datasheet > 98ULPA877A

98ULPA877A

更新时间： 2023-12-20 18:44:15

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
15页	362K
描述
1.8V Low-Power Wide-Range Frequency Clock Driver

阅读下载

获取价格

如果您发现信息不准确，欢迎纠错

98ULPA877A 数据手册

ICS98ULPA877A

Timing Requirements

Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;

Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)

CONDITIONS

PARAMETER

SYMBOL

freq_op

MIN

MAX UNITS

Max clock frequency

410

MHz

1.8V+0.1V @ 25°C

Application Frequency

Range

freq_App

d_tin

1.8V+0.1V @ 25°C

160

Input clock duty cycle

CLK stabilization

T_STAB

µs

NOTE: The PLL must be able to handle spread spectrum induced skew.

NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not

required to meet the other timing parameters. (Used for low speed system debug.)

NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.

NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback

signal to its reference signal, within the value specificied by the Static Phase Offset (t∅), after power-up. During

normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock

of its feedback signal to its reference signal when CK and CK# go to a logic low state, enter the power-down mode

and later return to active operation. CK and CK# may be left floating after they have been driven low for one

complete clock cycle.

1177F—12/10/09

1...3 4 567 8 9...15

下载PDF

型号	品牌	描述	获取价格	数据表
98ULPA877AH	IDT	CABGA-52, Tray	获取价格
98ULPA877AHI-T	IDT	PLL Based Clock Driver, 98ULPA Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, PL	获取价格
98ULPA877AHLF-T	IDT	PLL Based Clock Driver, 98ULPA Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, RO	获取价格
98ULPA877AH-T	IDT	PLL Based Clock Driver, 98ULPA Series, 10 True Output(s), 0 Inverted Output(s), PBGA52, PL	获取价格
98ULPA877AKILF-T	IDT	PLL Based Clock Driver, 98ULPA Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, RO	获取价格
98ULPA877AKI-T	IDT	PLL Based Clock Driver, 98ULPA Series, 10 True Output(s), 0 Inverted Output(s), PQCC40, PL	获取价格