ICS97U870
Advance Information
Pin Descriptions
Terminal
Name
Electrical
Characteristics
Description
AGND
Analog Ground
Analog power
Ground
1.8 V nominal
ꢀDD
CLK_INT
CLK_INC
FB_INT
Clock input with a (10K-100K Ohm) pulldown resistor
Complentary clock input with a (10K-100K Ohm) pulldown resistor
Feedback clock input
Difꢁerential input
Difꢁerential input
Difꢁerential input
FB_INC
FB_OUTT
FB_OUTC
OE
Complementary feedback clock input
Feedback clock output
Difꢂerential input
Difꢂerential output
Difꢂerential output
LVCMOS input
LVCMOS input
Ground
Complementary feedback clock output
Output Enable (Asynchronous)
OS
Output Select (tied to GND or V00ꢀ)
GND
VDDQ
Ground
Logic and output power
Clock outputs
1.8V nominal
CLKT[0:9]
CLKC[0:9]
NB
Difꢂerential outputs
Difꢂerential outputs
Complementary clock outputs
No ball
The PLL clock buffer, ICS97U870, is designed for aVꢀꢀꢁof 1.8ꢂ, a ꢃꢀꢀ of 1.8V and diꢄerentiaꢅ data input and output
levels. Package options incꢅude a pꢅastic 52-ballVFBGA and a 40-pin MLꢆ.
ICS97U870 is a zero delay buffer that distributes a diꢇerential cꢅock input pair(CLK_INꢈ, CLK_INC) to ten differentiaꢅ
pair of clock outputs(CLKT[0:9], CLKC[0ꢉ9ꢊ) and one differential pair feedback cꢅock outputs(FB_OUTꢈ, FBOUTC).
The clock outputs are controlledby the input cꢅocks(CLK_INꢈ, CLK_INC), thefeedbackclocks(FB_INꢈ, FB_ꢋNC), the
ꢌCMOS programpins(OE, OS) and the Anaꢅog Powerinput(ꢃDD)ꢍWhen OE isꢅow, the outputs(except FB_OUTT/
FB_OUTC) are disabled while the internal PLL continues to maintain its ꢅocked-in frequency. OS(Output Select) is a
program pin that must be tied to GND orVꢀꢀꢁ.When OS is high, OE will function as described aboveꢍWhen OS islow,
OE has no eꢄect on CLKT7/CLKC7(they arefreerunning in additionto FB_OUTT/FB_OUTC)ꢍWhen ꢃꢀꢀ is grounded,
the PLL is turned oꢇ and bypassed for test purposesꢍ
When both clock signals(CLK_INꢈ, CLK_INC) are logic low, the device will enter a low power modeꢍ An input logic
detection circuit on the diꢇerentiaꢅ inputs, independent from the input buꢇers, wilꢅ detectthe logic ꢅow ꢅeveꢅ and perꢎorm
a low power state where aꢅl outputs, the feedback andthe PLL are OFꢏWhen the inputs transition frꢐm both being logic
low to being difꢑerential signals, the PLL will be turned back on, the inputs and outputs wiꢅꢅ be enabled and the PLL
will obtain phase ꢅock between thefeedbackclock pair(FB_INꢈ, FB_INC)andthe inputcꢅockpair(CLK_INꢈ, CLK_ꢋNC)
within the specified stabiꢅization time tꢒꢓꢔꢕ
The PLL in ICS97U870 clock driver uses the input cꢅocks(CLK_INꢈ, CLK_INC) and the feedback clocks(FB_INꢈ,
FB_INC) toprovidehigh-peꢖormance, low-skew, lꢗꢘ-jitteroutputdiꢄerentialclocks(CLKT[0ꢉ9], CLKC[0:9])ꢍ ICS97U870
is also able to track Spread Spectrum Cꢅocking(SSC) fꢙr reduced EMI.
ICS97U870 is characterizedfor operation from 0°C to 70°Cꢍ
0817ꢀ07/07/03
2
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