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950602CFLF PDF预览

950602CFLF

更新时间: 2024-01-17 14:19:59
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
18页 233K
描述
SSOP-48, Tube

950602CFLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:0.300 INCH, GREEN, MO-118, SSOP-48针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:15.875 mm湿度敏感等级:1
端子数量:48最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260主时钟/晶体标称频率:14.32 MHz
认证状态:Not Qualified座面最大高度:2.8 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

950602CFLF 数据手册

 浏览型号950602CFLF的Datasheet PDF文件第2页浏览型号950602CFLF的Datasheet PDF文件第3页浏览型号950602CFLF的Datasheet PDF文件第4页浏览型号950602CFLF的Datasheet PDF文件第5页浏览型号950602CFLF的Datasheet PDF文件第6页浏览型号950602CFLF的Datasheet PDF文件第7页 
Integrated  
Circuit  
ICS950602  
Systems, Inc.  
Programmable Timing Control Hub™ for PII/III™  
Recommended Application:  
Pin Configuration  
VIA Mobile PL133T and PLE133T Chipsets.  
GND  
*FS2/REF1  
REF0  
Vtt_PWRGD#  
VDDREF  
GND  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
CPUCLK0  
CPUCLK1  
VDDCPU_2.5  
VDDCPU_3.3  
CPUCLKT  
CPUCLKC  
GND  
RESET#  
I REF  
SDRAM6  
GND  
SDRAM0  
SDRAM1  
VDDSDRAM  
SDRAM2  
SDRAM3  
GND  
SDRAM4  
SDRAM5  
VDDSDRAM  
AVDD48  
Output Features:  
2 - CPU clocks @ 2.5V  
1 - Pairs of differential CPU clocks @ 3.3V  
7 - PCI including 1 free running @ 3.3V  
7 - SDRAM @ 3.3V  
1 - 48MHz @ 3.3V fixed  
1 - 24_48MHz selectable @ 3.3V  
2 - REF @ 3.3V, 14.318MHz  
X1  
X2  
VDDPCI  
*FS4/PCICLK_F  
*FS3/PCICLK0  
GND  
PCICLK1  
PCICLK2  
PCICLK3  
PCICLK4  
PCICLK5  
SDRAM_IN  
*CPU_STOP#  
*PCI_STOP#  
*PD#  
Features/Benefits:  
Programmable output frequency.  
Programmable output divider ratios.  
Programmable output rise/fall time.  
Programmable output skew.  
Programmable spread percentage for EMI control.  
Watchdog timer technology to reset system  
if system malfunctions.  
**MULTISEL  
GND  
48MHz/FS0*  
24_48MHz/FS1*  
SCLK  
SDATA  
Programmable watch dog safe frequency.  
Support I2C Index read/write and block read/write  
operations.  
48-Pin SSOP & TSSOP  
Uses external 14.318MHz crystal.  
* Internal Pull-up resistor of 120K to VDD  
Key Specifications:  
** these inputs have 120K internal pull-down  
to GND  
CPU Output Jitter <200ps  
CPU Output Skew <175ps  
PCI to PCI Output Skew <500ps  
Block Diagram  
Host Swing Select Functions  
Board Target  
Trace/Term Z  
Reference R,  
Iref = VDD/(3*Rr)  
Output  
Current  
MULTISEL0  
Voh @ Z  
Rr = 221 1%,  
Iref = 5.00mA  
0
1
50 ohms  
50 ohms  
Ioh = 4* I REF 1.0V @ 50  
Ioh = 6* I REF 0.7V @ 50  
Rr = 475 1%,  
Iref = 2.32mA  
0469B—12/18/02  

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