Datasheet > 93LC56A-I/STRVA

93LC56A-I/STRVA

更新时间： 2024-01-23 13:04:42

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数	文件大小	规格书
36页	899K
描述
EEPROM, 256X8, Serial, CMOS, PDSO8

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技术参数
数据手册

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93LC56A-I/STRVA 技术参数

生命周期：	Active	包装说明：	TSSOP,
Reach Compliance Code：	compliant	风险等级：	5.59
其他特性：	1000000 ERASE/WRITE CYCLES MIN; DATA RETENTION > 200 YEARS	最大时钟频率 (fCLK)：	2 MHz
数据保留时间-最小值：	200	JESD-30 代码：	R-PDSO-G8
长度：	4.4 mm	内存密度：	2048 bit
内存集成电路类型：	EEPROM	内存宽度：	8
功能数量：	1	端子数量：	8
字数：	256 words	字数代码：	256
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	256X8
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行：	SERIAL	筛选级别：	TS 16949
座面最大高度：	1.2 mm	串行总线类型：	MICROWIRE
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	3 mm
最长写入周期时间 (tWC)：	6 ms	Base Number Matches：	1

93LC56A-I/STRVA 数据手册

93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C

2.3

Data Protection

2.0

FUNCTIONAL DESCRIPTION

All modes of operation are inhibited when VCC is below

a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices

or 3.8V for ‘93C’ devices.

When the ORG pin (93XX56C) pin is connected to

VCC, the (x16) organization is selected. When it is

connected to ground, the (x8) organization is selected.

Instructions, addresses and write data are clocked into

the DI pin on the rising edge of the clock (CLK). The DO

pin is normally held in a High-Z state except when read-

ing data from the device, or when checking the Ready/

Busy status during a programming operation. The

Ready/Busy status can be verified during an Erase/

Write operation by polling the DO pin; DO low indicates

that programming is still in progress, while DO high

indicates the device is ready. DO will enter the High-Z

state on the falling edge of CS.

The EWEN and EWDS commands give additional

protection against accidentally programming during

normal operation.

Note:

For added protection, an EWDS command

should be performed after every write

operation and an external 10 kpull-down

protection resistor should be added to the

CS pin.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWENinstruction must be

performed before the initial ERASEor WRITEinstruction

can be executed.

2.1

Start Condition

The Start bit is detected by the device if CS and DI are

both high with respect to the positive edge of CLK for

the first time.

Block Diagram

VCC

VSS

Before a Start condition is detected, CS, CLK and DI

may change in any combination (except to that of a

Start condition), without resulting in any device

operation (Read, Write, Erase, EWEN, EWDS, ERAL

or WRAL). As soon as CS is high, the device is no

longer in Standby mode.

Memory

Array

Address

Decoder

Address

Counter

An instruction following a Start condition will only be

executed if the required opcode, address and data bits

for any particular instruction are clocked in.

Output

Buffer

Data Register

Note:

When preparing to transmit an instruction,

either the CLK or DI signal levels must be

at a logic low as CS is toggled active high.

Mode

Decode

Logic

ORG*

2.2

Data In/Data Out (DI/DO)

It is possible to connect the Data In and Data Out pins

together. However, with this configuration it is possible

for a “bus conflict” to occur during the “dummy zero”

that precedes the read operation if A0 is a logic high

level. Under such a condition the voltage level seen at

Data Out is undefined and will depend upon the relative

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of A0,

the higher the voltage at the Data Out pin. In order to

limit this current, a resistor should be connected

between DI and DO.

Clock

CLK

*ORG input is not available on A/B devices

DS21794G-page 6

 2003-2011 Microchip Technology Inc.

1...3 4 567 8 9...36

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