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93C56A-I/PG

更新时间： 2024-01-09 06:07:57

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
12页	169K
描述
256 X 8 MICROWIRE BUS SERIAL EEPROM, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8

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技术参数
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93C56A-I/PG 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	0.150 INCH, PLASTIC, SOIC-8	针数：	8
Reach Compliance Code：	unknown	Factory Lead Time：	6 weeks
风险等级：	5.65	其他特性：	10K ERASE/WRITE CYCLES MIN; DATA RETENTION > 40 YEARS
备用内存宽度：	16	最大时钟频率 (fCLK)：	2 MHz
数据保留时间-最小值：	40	耐久性：	1000000 Write/Erase Cycles
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
内存密度：	2048 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端子数量：	8	字数：	256 words
字数代码：	256	工作模式：	SYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-40 °C
组织：	256X8	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	串行总线类型：	MICROWIRE
最大待机电流：	0.0001 A	子类别：	EEPROMs
最大压摆率：	0.004 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
最长写入周期时间 (tWC)：	1 ms	写保护：	SOFTWARE
Base Number Matches：	1

93C56A-I/PG 数据手册

93C56A/B

3.2

Data IN (DI) and Data Out (DO)

3.0

FUNCTIONAL DESCRIPTION

Instructions, addresses, and write data are clocked into

the DI pin on the rising edge of the clock (CLK).The DO

pin is normally held in a HIGH-Z state except when

reading data from the device, or when checking the

READY/BUSY status during a programming operation.

The READY/BUSY status can be veriﬁed during an

ERASE/WRITE operation by polling the DO pin; DO

low indicates that programming is still in progress, while

DO high indicates the device is ready.The DO will enter

the HIGH-Z state on the falling edge of the CS.

It is possible to connect the Data In (DI) and Data Out

(DO) pins together. However, with this conﬁguration, if

A0 is a logic-high level, it is possible for a “bus conﬂict”

to occur during the “dummy zero” that precedes the

READ operation. Under such a condition, the voltage

level seen at DO is undeﬁned and will depend upon the

relative impedances of DO and the signal source driv-

ing A0.The higher the current sourcing capability of A0,

the higher the voltage at the DO pin.

3.3

Data Protection

3.1

START Condition

During power-up, all programming modes of operation

are inhibited until Vcc has reached a level greater than

3.8V. During power-down, the source data protection

circuitry acts to inhibit all programming modes when

Vcc has fallen below 3.8V at nominal conditions.

The START bit is detected by the device if CS and DI

are both high with respect to the positive edge of CLK

for the ﬁrst time.

Before a START condition is detected, CS, CLK, and DI

may change in any combination (except to that of a

START condition), without resulting in any device oper-

ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,

and WRAL). As soon as CS is high, the device is no

longer in the standby mode.

The ERASE/WRITE Disable (EWDS) and ERASE

WRTE Enable (EWEN) commands give additional pro-

tection against accidentally programming during nor-

mal operation.

After power-up, the device is automatically in the

EWDS mode.Therefore, an EWEN instruction must be

performed before any ERASE or WRITE instruction

can be executed.

An instruction following a START condition will only be

executed if the required amount of opcode, address

and data bits for any particular instruction is clocked in.

After execution of an instruction (i.e., clock in or out of

the last required address or data bit) CLK and DI

become don't care bits until a new START condition is

detected.

FIGURE 3-1: SYNCHRONOUS DATA TIMING

VIH

TCSS

TCKH

TCKL

VIL

VIH

TCSH

CLK

VIL

TDIS

TDIH

VIH

VIL

TCZ

TPD

VOH

(READ)

TCZ

VOL

VOH

TSV

(PROGRAM)

STATUS VALID

VOL

Note: AC Test Conditions: VIL = 0.4V, VIH = 2.4V.

DS21206B-page 4

Preliminary

1998 Microchip Technology Inc.

1 2 345 6 7...12

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