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93AA46A-TI/MSGX PDF预览

93AA46A-TI/MSGX

更新时间: 2024-02-16 14:54:01
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 98K
描述
128 X 8 MICROWIRE BUS SERIAL EEPROM, PDSO8, LEAD FREE, PLASTIC, MO-187, MSOP-8

93AA46A-TI/MSGX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Not Recommended零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.42
Is Samacsys:N其他特性:100K ERASE/WRITE CYCLES MIN; DATA RETENTION > 40 YEARS
备用内存宽度:8最大时钟频率 (fCLK):2 MHz
数据保留时间-最小值:200耐久性:1000000 Write/Erase Cycles
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm内存密度:1024 bit
内存集成电路类型:EEPROM内存宽度:16
湿度敏感等级:1功能数量:1
端子数量:8字数:64 words
字数代码:64工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64X16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):260电源:2/5 V
认证状态:Not Qualified筛选级别:TS 16949
座面最大高度:1.75 mm串行总线类型:MICROWIRE
最大待机电流:0.00003 A子类别:EEPROMs
最大压摆率:0.001 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.91 mm最长写入周期时间 (tWC):10 ms
写保护:SOFTWAREBase Number Matches:1

93AA46A-TI/MSGX 数据手册

 浏览型号93AA46A-TI/MSGX的Datasheet PDF文件第2页浏览型号93AA46A-TI/MSGX的Datasheet PDF文件第3页浏览型号93AA46A-TI/MSGX的Datasheet PDF文件第4页浏览型号93AA46A-TI/MSGX的Datasheet PDF文件第6页浏览型号93AA46A-TI/MSGX的Datasheet PDF文件第7页浏览型号93AA46A-TI/MSGX的Datasheet PDF文件第8页 
93AA46/56/66  
2.8  
Erase All (ERAL)  
2.9  
Write All (WRAL)  
The ERAL instruction will erase the entire memory  
array to the logical “1” state. The ERAL cycle is identical  
to the ERASE cycle except for the different opcode. The  
ERAL cycle is completely self-timed and commences at  
the falling edge of the CS. Clocking of the CLK pin is not  
necessary after the device has entered the self clocking  
mode. The ERAL instruction is guaranteed at 5V ±  
10%.  
The WRALinstruction will write the entire memory array  
with the data specified in the command. The WRAL  
cycle is completely self-timed and commences at the  
falling edge of the CS. Clocking of the CLK pin is not  
necessary after the device has entered the self clocking  
mode. The WRAL command does include an auto-  
matic ERAL cycle for the device. Therefore, the WRAL  
instruction does not require an ERAL instruction but the  
chip must be in the EWEN status. The WRAL instruc-  
tion is guaranteed at 5V ± 10%.  
The DO pin indicates the READY/BUSY status of the  
device if CS is brought high after a minimum of 250 ns  
low (TCSL) and before the entire write cycle is complete.  
The DO pin indicates the READY/BUSY status of the  
device if CS is brought high after a minimum of 250 ns  
low (TCSL).  
The ERAL cycle takes (8 ms typical).  
The WRAL cycle takes 16 ms typical.  
FIGURE 2-1: SYNCHRONOUS DATA TIMING  
VIH  
CS  
TCSS  
TCKH  
TCKL  
VIL  
TCSH  
VIH  
CLK  
DI  
VIL  
TDIH  
TDIS  
VIH  
VIL  
TCZ  
TPD  
T PD  
VOH  
DO  
(READ)  
T CZ  
VOL  
VOH  
TSV  
DO  
(PROGRAM)  
STATUS VALID  
VOL  
FIGURE 2-2: READ TIMING  
TCSL  
CS  
CLK  
DI  
1
1
0
• A  
• • •  
A0  
n
TRI-STATE  
DO  
0
Dx  
• • •  
D0  
Dx*  
• • •  
D0  
Dx*  
• • •  
D0  
Tri-State is a registered trademark of National Semiconductor Incorporated.  
1996 Microchip Technology Inc.  
DS20067G-page 5  

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