Datasheet > 存储 > EEPROM> 93AA46A-I/ST

93AA46A-I/ST

更新时间： 2024-02-15 02:04:19

品牌	Logo	应用领域
美国微芯 - MICROCHIP		存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
24页	388K
描述
1K Microwire Compatible Serial EEPROM

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技术参数
数据手册

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93AA46A-I/ST 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	零件包装代码：	SOIC
包装说明：	SOP, SOP8,.25	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.42
Is Samacsys：	N	其他特性：	100K ERASE/WRITE CYCLES MIN; DATA RETENTION > 40 YEARS
备用内存宽度：	8	最大时钟频率 (fCLK)：	2 MHz
数据保留时间-最小值：	200	耐久性：	1000000 Write/Erase Cycles
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.9 mm	内存密度：	1024 bit
内存集成电路类型：	EEPROM	内存宽度：	16
湿度敏感等级：	1	功能数量：	1
端子数量：	8	字数：	64 words
字数代码：	64	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64X16	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	电源：	2/5 V
认证状态：	Not Qualified	筛选级别：	TS 16949
座面最大高度：	1.75 mm	串行总线类型：	MICROWIRE
最大待机电流：	0.00003 A	子类别：	EEPROMs
最大压摆率：	0.001 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	1.8 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	3.91 mm	最长写入周期时间 (tWC)：	10 ms
写保护：	SOFTWARE	Base Number Matches：	1

93AA46A-I/ST 数据手册

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.3

Data Protection

2.0

FUNCTIONAL DESCRIPTION

All modes of operation are inhibited when VCC is below

a typical voltage of 1.5V for '93AA' and '93LC' devices

or 3.8V for '93C' devices.

When the ORG* pin is connected to VCC, the (x16)

organization is selected. When it is connected to

ground, the (x8) organization is selected. Instructions,

addresses and write data are clocked into the DI pin on

the rising edge of the clock (CLK). The DO pin is

normally held in a HIGH-Z state except when reading

data from the device, or when checking the READY/

BUSY status during a programming operation. The

READY/BUSY status can be verified during an Erase/

Write operation by polling the DO pin; DO low indicates

that programming is still in progress, while DO high

indicates the device is ready. DO will enter the HIGH-Z

state on the falling edge of CS.

The EWEN and EWDS commands give additional

protection against accidentally programming during

normal operation.

Note: For added protection, an EWDS command

should be performed after every write

operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWENinstruction must be

performed before the initial ERASEor WRITEinstruction

can be executed.

2.1

Start Condition

Block Diagram

The Start bit is detected by the device if CS and DI are

both high with respect to the positive edge of CLK for

the first time.

VCC

VSS

Address

Decoder

Memory

Array

Before a Start condition is detected, CS, CLK, and DI

may change in any combination (except to that of a

Start condition), without resulting in any device

operation (READ, WRITE, ERASE, EWEN, EWDS,

ERAL, or WRAL). As soon as CS is high, the device is

no longer in Standby mode.

Address

Counter

An instruction following a Start condition will only be

executed if the required opcode, address and data bits

for any particular instruction are clocked in.

Output

Buffer

Data Register

Mode

Decode

Logic

2.2

Data In/Data Out (DI/DO)

ORG*

It is possible to connect the Data In and Data Out pins

together. However, with this configuration it is possible

for a “bus conflict” to occur during the “dummy zero”

that precedes the READ operation, if A0 is a logic high

level. Under such a condition the voltage level seen at

Data Out is undefined and will depend upon the relative

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of A0,

the higher the voltage at the Data Out pin. In order to

limit this current, a resistor should be connected

between DI and DO.

Clock

CLK

*ORG input is not available on A/B devices

 2003 Microchip Technology Inc.

DS21749D-page 5

1 2 3 456 7 8...24

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