Datasheet > 935353606557

935353606557

更新时间： 2024-09-21 20:51:59

品牌	Logo	应用领域
恩智浦 - NXP		外围集成电路
页数	文件大小	规格书
90页	1879K
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RISC Microprocessor

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935353606557 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.72
uPs/uCs/外围集成电路类型：	MICROPROCESSOR, RISC	Base Number Matches：	1

935353606557 数据手册

Document Number S32V234

Rev. 8, 01/2019

NXP Semiconductors

Data Sheet: Technical Data

S32V234

S32V234 Data Sheet

Features

• Safety concept

– ISO 26262, ASIL level target

• ARM® Cortex®-A53, 64-bit CPU

– Up to 1000 MHz Quad ARM Cortex-A53

– 32 KB/32 KB I-/D- L1 Cache

– NEON MPE co-processor

– Measures to detect faults in memory and logic

– Measures to detect single point and latent faults

– Quantitative out of context analysis of functional

safety (FMEDA) tailored to application specifics

– Safety manual and FMEDA report available

– Dual precision FPU

– 2 clusters with 2 CPUs and 256 KB L2 cache each

– Memory Management Unit

• Security

– GIC Interrupt Controller

– ECC/parity error support for its memories

– Generic timers

– Fault encapsulation by hardware for redundant

executed application software on multiple core

cluster

– CSE with 16 KB of on-chip Secure RAM and ROM.

– Secure vs non-secure applications separation

supported via ARM v8 exception level support in

the ARM Cortex A53 clusters and its extension via

XRDC on chip level.

– Boot from NOR flash with AES-128 (CTR)

– On-Chip One-Time Programmable element

Controller (OCOTP_CTRL) with on chip electrical

fuse array.

• ARM Cortex-M4, 32-bit CPU

– Up to 133 MHz

– 16 KB/16 KB I-/D- L1 Cache

– 32+32 KB tightly coupled memory (TCM)

– ECC/parity support for its memories

– System JTAG Controller (SJC)

• Debug functionality

– Standard JTAG and Compact JTAG

– 16-bit Trace port, Serial Wire Output port

• Clocks

– Phase Locked Loops (PLLs)

– 1 external crystal oscillator (FXOSC)

– 1 FIRC oscillator

• Timers

– General purpose timers (FTM)

– Two Periodic Interrupt Timer (PIT)

– IEEE 1588 Timers (part of Ethernet Subsystem)

• System protection and power management features

– Flexible run modes to consume low power based on

application needs

• Analog

– Peripheral clock enable register can disable clocks to

unused modules, thereby reducing currents

– Power gating of unused A53 cores and GPU

– Low and high voltage warning and detect

– Hardware CRC module to support fast cyclic

redundancy checks (CRC)

– 120-bit unique chip identifier

– Hardware watchdog

– eDMA controller with 32 channels (with

DMAMUX)

– Extended Resource Domain Controller

– 1x 12-bit 1.8 V SAR ADC with self-test

• Communications

– UART(w/ LIN2.1l)

– Serial peripheral interface (SPI)

– I2C blocks

– PCI express 2.0 with endpoint and root complex

support

– LFAST serial link

– 1 GBit Ethernet with PTP IEEE 1588

– FD-CAN

– FlexRay Dual Channel, Version 2.1 RevA

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

12 3 4 5 6 7...90

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